Bora Guvendik 43c3109696 soc/intel/skylake: Use ITSS common code ... This patch uses common ITSS library to setup itss irq. Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19244 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-04-28 16:32:20 +02:00
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dptf	soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control	2016-11-07 20:41:36 +01:00
cpu.asl
globalnvs.asl	intel/skylake: Add support to enable wake-on-usb attach/detach	2016-10-26 08:33:37 +02:00
gpio.asl	soc/intel/skylake: Add SKL SOC PCH H GPIO support	2017-03-09 16:38:40 +01:00
ipu.asl	soc/intel/skylake: Add ASL entries for IMGU and CIO2 devices	2017-04-19 16:17:57 +02:00
irqlinks.asl	soc/intel/skylake: Use common PCR module	2017-04-10 20:04:01 +02:00
lpc.asl
pch.asl	soc/intel/skylake: Use ITSS common code	2017-04-28 16:32:20 +02:00
pch_hda.asl
pci_irqs.asl	soc/intel/skylake: Add SATA interrupt for APIC mode	2017-01-19 07:28:15 +01:00
pcie.asl
pcr.asl	soc/intel/skylake: Use common PCR module	2017-04-10 20:04:01 +02:00
platform.asl
pmc.asl
scs.asl	soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller	2017-03-10 11:19:04 +01:00
serialio.asl	soc/intel/skylake: Correct address of I2C5 Device	2016-08-04 16:12:13 +02:00
sleepstates.asl
smbus.asl	Remove extra newlines from the end of all coreboot files.	2016-07-31 18:19:33 +02:00
systemagent.asl	soc/intel/skylake: Clean up SoC ASL code.	2016-08-08 18:31:38 +02:00
xhci.asl	soc/intel/skylake: Enable XHCI clock gate control in ACPI	2017-04-07 21:44:29 +02:00