Duncan Laurie 9fd7c0f18e baytrail: Add SOC thermal settings ... Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2014-05-15 05:09:27 +02:00
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arch	SeaBIOS: Fix cpp use	2014-05-11 08:51:54 +02:00
console	console: Fix UART selection prompt	2014-04-30 23:47:28 +02:00
cpu	cpu/intel: Add CPU socket rPGA988B	2014-05-13 21:58:16 +02:00
device	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
drivers	src/drivers/pc80: Remove empty struct keyboard	2014-05-13 10:03:51 +02:00
ec	chromeec: add function to reboot on unexpected image	2014-05-13 21:01:52 +02:00
include	intel: Drop obsolete comments on MTRR usage	2014-05-14 07:30:20 +02:00
lib	baytrail: snapshot power state in romstage	2014-05-13 16:11:04 +02:00
mainboard	rambi: Add ACPI devices and interrupts for codec and ALS	2014-05-15 05:06:38 +02:00
northbridge	intel: Drop obsolete comments on MTRR usage	2014-05-14 07:30:20 +02:00
soc	baytrail: Add SOC thermal settings	2014-05-15 05:09:27 +02:00
southbridge	southbridge/amd/cimx/sb800: Unused func smbus_delay()	2014-05-14 21:48:27 +02:00
superio	src/*: Remove the last remnants of struct keyboard	2014-05-13 12:14:34 +02:00
vendorcode	Declare get_write_protect_state() without ChromeOS	2014-05-08 16:25:30 +02:00
Kconfig	Arch-level Kconfig menu cleanup	2014-05-10 14:32:26 +02:00