Jens Drenhaus fe66a0760c soc/cavium: dynamic UART initialization for cavium cn8100 ... Now only those UARTs that are enabled in devicetree.cb are initialized. Tested on Opencellular Elgon. Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com> Reviewed-on: https://review.coreboot.org/28975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>		2018-10-10 16:37:38 +00:00
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include	soc/cavium/cn81xx/spi: Add function to return SPI clock	2018-09-30 03:04:53 +00:00
bl31_plat_params.c	soc/cavium/cn81xx: Use ATF from blobs repo	2018-07-30 18:47:26 +00:00
bootblock.c
bootblock_custom.S	soc/cavium/bootblock: Get rid of register X1	2018-07-30 18:46:41 +00:00
cbmem.c	soc/cavium/cn81xx: Fix minor things	2018-08-10 23:24:56 +00:00
chip.h
clock.c	Coverity: Fix CID1393976	2018-07-12 15:22:06 +00:00
cpu.c	soc/cavium: Add secondary CPU support	2018-07-10 07:07:09 +00:00
cpu_secondary.S	soc/cavium: Add secondary CPU support	2018-07-10 07:07:09 +00:00
ecam0.c	soc/cavium: Add PCI support	2018-07-19 13:57:24 +00:00
gpio.c	soc/cavium: Fix overflow before widen	2018-07-16 14:41:10 +00:00
Kconfig	soc/cn81xx: Add vboot support	2018-08-24 12:29:28 +00:00
Makefile.inc	soc/cn81xx: Add vboot support	2018-08-24 12:29:28 +00:00
mmu.c
reset.c	soc/cn81xx: Add vboot support	2018-08-24 12:29:28 +00:00
sdram.c	soc/cavium: Enable DRAM test	2018-07-23 06:36:21 +00:00
soc.c	soc/cavium: dynamic UART initialization for cavium cn8100	2018-10-10 16:37:38 +00:00
spi.c	soc/cavium/cn81xx/spi: Add function to return SPI clock	2018-09-30 03:04:53 +00:00
timer.c	arm64: Remove set_cntfrq() function	2018-08-10 04:16:06 +00:00
twsi.c
uart.c	soc/cavium: Clean uart code	2018-07-10 07:03:56 +00:00