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soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
##
## This file is part of the coreboot project.
##
drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driver Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25 07:11:04 +01:00
## Copyright (C) 2014 - 2018 Intel Corporation.
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOC_INTEL_DENVERTON_NS
bool
help
Intel Denverton-NS SoC support
if SOC_INTEL_DENVERTON_NS
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
soc/intel/.../Kconfig: Move GPIO debug option into debug menu Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the Debugging menu. Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-13 22:06:40 +01:00
select DEBUG_GPIO
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select PLATFORM_USES_FSP2_0
select IOAPIC
select HAVE_SMI_HANDLER
select CACHE_MRC_SETTINGS
select PARALLEL_MP
soc/intel/denverton_ns: port gpio to intelblock The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-29 11:36:21 +02:00
select PCR_COMMON_IOSF_1_0
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
select SMP
src/*/intel/: clarify Kconfig options regarding IFD HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06 00:34:28 +02:00
select INTEL_DESCRIPTOR_MODE_CAPABLE
soc/intel/denverton_ns: Enable ACPI using intelblock - Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-05 11:24:45 +02:00
select COMMON_FADT
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
select SOC_INTEL_COMMON_BLOCK
soc/intel/denverton_ns: Enable common code for CPU Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24927 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-08 14:03:28 +01:00
select SOC_INTEL_COMMON_BLOCK_CPU
soc/intel/denverton_ns: Enable ACPI using intelblock - Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-05 11:24:45 +02:00
select SOC_INTEL_COMMON_BLOCK_ACPI
soc/intel/denverton_ns: Enable common block PMC Mainly update headers to build. Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove function configuring the global reset through PMC base. On denverton the global reset lock is not in PMC base but in the PCI registers so this code cannot be shared. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-14 16:15:26 +02:00
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
soc/intel/denverton_ns: port gpio to intelblock The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-29 11:36:21 +02:00
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driver Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25 07:11:04 +01:00
select UDK_2015_BINDING
soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE * Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06 22:12:53 +02:00
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
soc/intel/common/systemagent: Add Kconfig guard Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to some value which can't be overriden outside of soc/intel/common. So adding a non-SoC platform thats uses code from soc/intel/common is not possible. TEST=build test on wip platform Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-12-30 18:58:47 +01:00
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
config FSP_T_ADDR
src: capitalize 'RAM' Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-20 19:41:17 +01:00
hex "Intel FSP-T (temp RAM init) binary location"
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
depends on ADD_FSP_BINARIES && FSP_CAR
default 0xfff30000
help
The memory location of the Intel FSP-T binary for this platform.
config FSP_M_ADDR
hex "Intel FSP-M (memory init) binary location"
depends on ADD_FSP_BINARIES
default 0xfff32000
help
The memory location of the Intel FSP-M binary for this platform.
config FSP_S_ADDR
hex "Intel FSP-S (silicon init) binary location"
depends on ADD_FSP_BINARIES
default 0xfffc3000
help
The memory location of the Intel FSP-S binary for this platform.
# CAR memory layout on DENVERTON_NS hardware:
## CAR base address - 0xfef00000
## CAR size 1MB - 0x100 (0xfff00)
## coreboot usage:
## DCACHE base - 0xfef00000
## DCACHE size - 0xb0000
## FSP usage:
## FSP base - 0xfefb0000
## FSP size - 0x50000 - 0x100 (0x4ff00)
config MAX_CPUS
int
default 16
soc/intel/denverton_ns: port gpio to intelblock The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-29 11:36:21 +02:00
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
config DCACHE_RAM_BASE
hex
default 0xfef00000
config DCACHE_RAM_SIZE
hex
default 0xb0000 if FSP_CAR
default 0x100000 if !FSP_CAR
config DCACHE_BSP_STACK_SIZE
hex
default 0x10000
soc/intel/denverton_ns: Enable common code for CPU Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24927 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-08 14:03:28 +01:00
config CPU_BCLK_MHZ
int
default 100
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
config SMM_TSEG_SIZE
hex
default 0x200000
config SMM_RESERVED_SIZE
hex
default 0x000000
config IQAT_ENABLE
bool "Enable IQAT"
default y
config IQAT_MEMORY_REGION_SIZE
depends on IQAT_ENABLE
hex
default 0x100000
help
Do not change this value
config HSUART_DEV
hex
default 0x1a
choice
prompt "UART mode selection"
default NON_LEGACY_UART_MODE
config NON_LEGACY_UART_MODE
bool "Non Legacy Mode"
help
Disable legacy UART mode
config LEGACY_UART_MODE
bool "Legacy Mode"
help
Enable legacy UART mode
endchoice
config ENABLE_HSUART
drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO It defaults to y to avoid having to select it per mainboard. But that makes a mess because it results in linker conflicts unless other UART drivers disable it explicitly. We try to be smarter about the default value for now. The real solu- tion would be to hardcode it per mainboard. But who knows which boards actually have it? Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29571 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-11 00:27:41 +01:00
depends on NON_LEGACY_UART_MODE
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-08-02 17:28:17 +02:00
bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE."
default n
select CONSOLE_SERIAL
select DRIVERS_UART
select DRIVERS_UART_8250MEM
config CONSOLE_UART_BASE_ADDRESS
depends on ENABLE_HSUART
hex "MMIO base address for UART"
default 0xd4000000
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x8000
config DENVERTON_NS_CAR_NEM_ENHANCED
bool "Enhanced Non-evict mode"
depends on !FSP_CAR
default y
select SOC_INTEL_COMMON_BLOCK_CAR
select INTEL_CAR_NEM_ENHANCED
help
A current limitation of NEM (Non-Evict mode) is that code and data sizes
are derived from the requirement to not write out any modified cache line.
With NEM, if there is no physical memory behind the cached area,
the modified data will be lost and NEM results will be inconsistent.
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
endif ## SOC_INTEL_DENVERTON_NS
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