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coreboot-kgpe-d16/src/soc/intel/apollolake/acpi/globalnvs.asl

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soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* NOTE: The layout of the GNVS structure below must match the layout in
* soc/intel/apollolake/include/soc/nvs.h !!!
*
*/
External (NVSA)
OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
intel/apollolake: Add support to enable google ChromeEC ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25 20:34:43 +02:00
/* Miscellaneous */
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
Offset (0x00),
intel/apollolake: Correct the offsets in gnvs Offsets start from 0 instead of 1. Fix this in the gnvs definitions. BUG=chrome-os-partner:54342 Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15180 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-14 18:35:04 +02:00
PCNT, 8, // 0x00 - Processor Count
PPCM, 8, // 0x01 - Max PPC State
LIDS, 8, // 0x02 - LID State
PWRS, 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
soc/intel/apollolake: Include _PTS, _WAK and _SWS Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-09 02:39:37 +02:00
PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
soc/intel/apollolake: Add NHLT table region to ACPI global nvs Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-04-01 00:41:30 +02:00
NHLA, 64, // 0x19 - 0x20 - NHLT Address
NHLL, 32, // 0x21 - 0x24 - NHLT Length
soc/intel/apollolake: Add PM methods to power gate PCIe This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-24 02:56:17 +02:00
PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
soc/intel/apollolake: Add PM methods to power gate SD card This implements dynamic generation of sdcard GpioInt in SSDT. GpioInt in SSDT generation is based on the card detect GPIO if it is provided by the mainboard in devicetree. This implements GNVS variable to store the address of sdcard cd pin. GNVS used to store rxstate of the sdcard cd pin to get card presence. Add _PS0/_PS3 methods to power gate the sd card controller in S0ix and runtime PM. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18496 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-02-25 00:37:30 +01:00
SCD0, 32, // 0x29 - 0x2D - SD_CD Address
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
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