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Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<!DOCTYPE html>
<html>
<head>
<title>Development</title>
</head>
<body>
Documentation: Fix links to Intel/documentation.html Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03 16:28:22 +01:00
<h1>Intel&reg; x86 coreboot/FSP Development Process</h1>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<p>
The x86 development process for coreboot is broken into the following components:
</p>
<ul>
Documentation: Fix links to Intel/documentation.html Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03 16:28:22 +01:00
<li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li>
<li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li>
</ul>
<p>
The development process has two main phases:
</p>
<ol>
<li>Minimal coreboot; This phase is single threaded</li>
<li>Adding coreboot features</li>
</ol>
Documentation: Fix links to Intel/documentation.html Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03 16:28:22 +01:00
<h2>Minimal coreboot</h2>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<p>
The combined steps below describe how to bring up a minimal coreboot for a
system-on-a-chip (SoC) and a development board:
</p>
<table>
<tr bgcolor="#ffffc0">
<td>The initial coreboot steps are single threaded!
The initial minimal FSP development is also single threaded.
Progress can speed up by adding more developers after the minimal coreboot/FSP
implementation reaches the payload.
</td>
</tr>
</table>
<ol>
<li>Get the necessary tools:
<ul>
<li>Linux: Use your package manager to install m4 bison flex and the libcurses development
package.
<ul>
<li>Ubuntu or other Linux distribution that use apt, run:
<pre><code>sudo apt-get install m4 bison flex libncurses5-dev
</code></pre>
</li>
</ul>
</li>
</ul>
</li>
<li>Build the cross tools for i386:
<ul>
<li>Linux:
<pre><code>make crossgcc-i386</code></pre>
To use multiple processors for the toolchain build (which takes a long time), use:
<pre><code>make crossgcc-i386 CPUS=N</code></pre>
where N is the number of cores to use for the build.
</li>
</ul>
</li>
<li>Get something to build:
<ol type="A">
<li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
<li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li>
<li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li>
</ol>
</li>
<li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
Documentation: Add x86 bootblock support Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13441 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 19:49:35 +01:00
<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
<li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
<li>Enable the serial port
<ol type="A">
<li>Power on, enable and configure GPIOs for the
<a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
</li>
<li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
support to romstage
</li>
</ol>
</li>
<li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
<li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li>
<li>Enable DRAM:
<ol type="A">
<li>Implement the SoC
<a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a>
Support
</li>
<li>Implement the board support to read the
<a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a>
</li>
</ol>
</li>
Documentation: x86 shadow ROM disable Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:28:06 +01:00
<li>Disable the
<a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
</li>
Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 21:19:13 +01:00
<li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<li>
Implement the .init routine for the
<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
structure which calls FSP SiliconInit
</li>
<li>
Start ramstage's
<a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
to display the PCI vendor and device IDs
</li>
<li>
Disable the
<a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
</li>
<li>
Implement the
<a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
</li>
Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 21:19:13 +01:00
<li>coreboot should now attempt to load the payload</li>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
</ol>
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<h2>Add coreboot Features</h2>
<p>
Most of the coreboot development gets done in this phase. Implementation tasks in this
phase are easily done in parallel.
</p>
<ul>
<li>Payload and OS Features:
<ul>
<li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
Documentation/Intel: More CorebootPayloadPkg documentation Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28 15:22:47 +01:00
<li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
</ul>
</li>
</ul>
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
<hr>
<table border="1">
<tr bgcolor="#c0ffc0">
<th colspan=3><h1>Features</h1></th>
</tr>
<tr bgcolor="#c0ffc0">
<th>SoC</th>
<th>Where</th>
<th>Testing</th>
</tr>
Documentation/Intel: More CorebootPayloadPkg documentation Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28 15:22:47 +01:00
<tr>
<td>8254 Programmable Interval Timer</td>
<td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
<td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
</tr>
<tr>
<td>8259 Programmable Interrupt Controller</td>
<td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
<td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
</tr>
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
<tr>
<td>Cache-as-RAM</td>
<td>
<a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
FSP binary:
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br>
Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
called from
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br>
Disable: FSP 1.1 TempRamExit called from
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
</td>
<td>FindFSP: POST code 0x90
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
is displayed<br>
Enable: POST code
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
is displayed<br>
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
</td>
</tr>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<tr>
<td>Memory Map</td>
<td>
Implement a device driver for the
<a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
</td>
<td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
</tr>
Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 21:19:13 +01:00
<tr>
<td>MTRRs</td>
<td>
Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br>
Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a>
</td>
<td>Set: Post code 0x91
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>)
is displayed by
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
Load: Post code 0x3C is displayed by
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br>
and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td>
</tr>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<tr>
<td>PCI Device Support</td>
<td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
<td>The device is detected by coreboot and usable by the payload</td>
</tr>
<tr>
<td>Ramstage state machine</td>
<td>
Implement the chip and domain operations to start the
<a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
processing
</td>
<td>
During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
for the PCI devices on the bus.
</td>
</tr>
Documentation: x86 shadow ROM disable Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:28:06 +01:00
<tr>
<td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
<td>
Disable: src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
</td>
<td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
</tr>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
<tr bgcolor="#c0ffc0">
<th>Board</th>
<th>Where</th>
<th>Testing</th>
</tr>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<tr>
<td>Device Tree</td>
<td>
<a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
the device tree processing<br>
<a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
<td>
List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
</td>
</tr>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
<tr>
<td>DRAM</td>
<td>
Load SPD data: src/soc/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
UPD Setup:
<ul>
<li>src/soc&lt;Vendor&gt;//&lt;Chip Family&gt;/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li>
<li>src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li>
</ul>
FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a>
</td>
<td>Select the following Kconfig values
<ul>
<li>DISPLAY_HOBS</li>
<li>DISPLAY_UPD_DATA</li>
</ul>
Testing successful if:
<ul>
<li>MemoryInit UPD values are correct</li>
<li>MemoryInit returns 0 (success) and</li>
<li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
is not displayed
</li>
</ul>
</td>
</tr>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
<tr>
<td>Serial Port</td>
<td>
SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
Enable: src/soc/mainboard/&lt;Board&gt;/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
</td>
<td>Debug serial output works</td>
</tr>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<tr bgcolor="#c0ffc0">
<th>Payload</th>
<th>Where</th>
<th>Testing</th>
</tr>
<tr>
<td>ACPI Tables</td>
<td>
SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
</td>
<td>Verified by payload or OS</td>
</tr>
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
<tr bgcolor="#c0ffc0">
<th>FSP</th>
<th>Where</th>
<th>Testing</th>
</tr>
<tr>
<td>TempRamInit</td>
<td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
<td>FSP binary found: POST code 0x90
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
is displayed<br>
TempRamInit successful: POST code
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
is displayed<br>
</td>
</tr>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
<tr>
<td>MemoryInit</td>
<td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br>
<a target="_blank" href="Board/board.html#SpdData">Board</a> support<br>
</td>
<td>Select the following Kconfig values
<ul>
<li>DISPLAY_HOBS</li>
<li>DISPLAY_UPD_DATA</li>
</ul>
Testing successful if:
<ul>
<li>MemoryInit UPD values are correct</li>
<li>MemoryInit returns 0 (success) and</li>
<li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
is not displayed
</li>
</ul>
</td>
</tr>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<tr>
<td>TempRamExit</td>
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
<td>src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<td>Post code 0x91
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
is displayed before calling TempRamExit by
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
Post code 0x39 is displayed by
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
</td>
</tr>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<tr>
<td>SiliconInit</td>
<td>
Implement the .init routine for the
<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
</td>
<td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
</tr>
<tr>
<td>FspNotify</td>
<td>
The code which calls FspNotify is located in
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
The fsp_notify_boot_state_callback routine is called three times as specified
by the BOOT_STATE_INIT_ENTRY macros below the routine.
</td>
<td>
The FspNotify routines are called during:
<ul>
<li>BS_DEV_RESOURCES - on exit</li>
<li>BS_PAYLOAD_LOAD - on exit</li>
<li>BS_OS_RESUME - on entry (S3 resume)</li>
</ul>
</td>
</tr>
Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:48:15 +01:00
</table>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<hr>
Documentation: x86 shadow ROM disable Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:28:06 +01:00
<p>Modified: 4 March 2016</p>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
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