2014-06-23 05:40:39 +02:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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2015-04-27 23:03:57 +02:00
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ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y)
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2014-08-26 11:31:28 +02:00
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IDBTOOL = util/rockchip/make_idb.py
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2014-06-23 05:40:39 +02:00
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#bootblock-y += bootblock.c
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bootblock-y += cbmem.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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endif
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2014-08-27 11:07:42 +02:00
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bootblock-y += timer.c
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rk3288: add clock module
Call rkclk_init() in bootblock stage.
apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz
arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz
l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz
aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9
Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209428
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-07-31 08:50:49 +02:00
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bootblock-y += clock.c
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2014-08-26 11:28:46 +02:00
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bootblock-y += spi.c
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2014-09-24 18:39:16 +02:00
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bootblock-y += gpio.c
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2014-09-27 06:02:27 +02:00
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bootblock-y += i2c.c
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2015-02-10 02:40:58 +01:00
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bootblock-$(CONFIG_SOFTWARE_I2C) += software_i2c.c
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2014-10-11 05:28:47 +02:00
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bootblock-y += rk808.c
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2014-09-24 18:39:16 +02:00
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verstage-y += spi.c
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verstage-y += timer.c
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2015-04-07 13:49:32 +02:00
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verstage-$(CONFIG_DRIVERS_UART) += uart.c
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2014-09-24 18:39:16 +02:00
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verstage-y += gpio.c
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verstage-y += clock.c
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2014-12-17 07:48:26 +01:00
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verstage-y += crypto.c
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2014-09-24 18:39:16 +02:00
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verstage-y += i2c.c
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2015-02-10 02:40:58 +01:00
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verstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c
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2014-06-23 05:40:39 +02:00
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romstage-y += cbmem.c
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romstage-y += timer.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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2014-07-31 05:34:40 +02:00
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romstage-y += i2c.c
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2015-02-10 02:40:58 +01:00
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romstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c
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rk3288: add clock module
Call rkclk_init() in bootblock stage.
apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz
arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz
l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz
aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9
Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209428
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-07-31 08:50:49 +02:00
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romstage-y += clock.c
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2014-08-26 12:22:08 +02:00
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romstage-y += gpio.c
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2014-08-26 11:28:46 +02:00
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romstage-y += spi.c
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2014-08-28 18:37:22 +02:00
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romstage-y += sdram.c
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2014-12-06 02:29:42 +01:00
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romstage-y += rk808.c
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2014-09-25 10:33:38 +02:00
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romstage-y += pwm.c
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2014-10-14 19:04:16 +02:00
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romstage-y += tsadc.c
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2014-08-26 12:22:08 +02:00
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2014-08-16 04:49:32 +02:00
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ramstage-y += soc.c
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2014-06-23 05:40:39 +02:00
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ramstage-y += cbmem.c
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ramstage-y += timer.c
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2014-07-31 05:34:40 +02:00
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ramstage-y += i2c.c
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2015-02-10 02:40:58 +01:00
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ramstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c
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rk3288: add clock module
Call rkclk_init() in bootblock stage.
apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz
arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz
l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz
aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9
Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209428
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-07-31 08:50:49 +02:00
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ramstage-y += clock.c
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2014-08-26 11:28:46 +02:00
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ramstage-y += spi.c
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2015-01-26 14:04:55 +01:00
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ramstage-y += sdram.c
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2014-08-26 12:22:08 +02:00
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ramstage-y += gpio.c
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2014-09-11 04:37:15 +02:00
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ramstage-y += rk808.c
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2014-09-25 10:33:38 +02:00
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ramstage-y += pwm.c
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2014-09-19 08:51:52 +02:00
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ramstage-y += vop.c
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ramstage-y += edp.c
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ramstage-y += display.c
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2014-06-23 05:40:39 +02:00
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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2014-08-26 11:31:28 +02:00
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2014-10-20 22:14:55 +02:00
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CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/
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2014-08-26 11:31:28 +02:00
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$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
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cp $< $@
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@printf "Generating: $(subst $(obj)/,,$(@))\n"
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@mkdir -p $(dir $@)
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@$(IDBTOOL) --from=$< --to=$@ --enable-align
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2015-04-27 23:03:57 +02:00
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endif
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