2012-11-27 19:36:06 +01:00
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/*
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2013-05-15 01:57:50 +02:00
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* This file is part of the coreboot project.
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2012-11-27 19:36:06 +01:00
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*
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2013-05-15 01:57:50 +02:00
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* Copyright (C) 2010 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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2012-11-27 19:36:06 +01:00
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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2013-05-15 01:57:50 +02:00
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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2012-11-27 19:36:06 +01:00
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*/
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2013-05-15 01:57:50 +02:00
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#ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H
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#define CPU_SAMSUNG_EXYNOS5250_CPU_H
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2013-05-14 22:32:33 +02:00
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#include <arch/io.h>
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#define DEVICE_NOT_AVAILABLE 0
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#define EXYNOS_PRO_ID 0x10000000
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/* Address of address of function that copys data from SD or MMC */
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#define EXYNOS_COPY_MMC_FNPTR_ADDR 0x02020030
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/* Address of address of function that copys data from SPI */
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#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
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/* Address of address of function that copys data through USB */
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#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
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/* Boot mode values */
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#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
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#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
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#define EXYNOS_I2C_SPACING 0x10000
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2012-11-27 19:36:06 +01:00
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/* EXYNOS5 */
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#define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */
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#define EXYNOS5_PRO_ID 0x10000000
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#define EXYNOS5_CLOCK_BASE 0x10010000
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#define EXYNOS5_POWER_BASE 0x10040000
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#define EXYNOS5_SWRESET 0x10040400
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#define EXYNOS5_SYSREG_BASE 0x10050000
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#define EXYNOS5_TZPC1_DECPROT1SET 0x10110810
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#define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000
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#define EXYNOS5_WATCHDOG_BASE 0x101D0000
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#define EXYNOS5_ACE_SFR_BASE 0x10830000
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#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
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#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
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#define EXYNOS5_GPIO_PART4_BASE 0x10D10000 /* V00..V37 */
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#define EXYNOS5_GPIO_PART5_BASE 0x10D100C0 /* V40..V47 */
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#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
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#define EXYNOS5_GPIO_PART1_BASE 0x11400000 /* A00..Y67 */
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#define EXYNOS5_GPIO_PART2_BASE 0x11400c00 /* X00..X37 */
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#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
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#define EXYNOS5_USBPHY_BASE 0x12130000
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#define EXYNOS5_USBOTG_BASE 0x12140000
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#define EXYNOS5_MMC_BASE 0x12200000
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#define EXYNOS5_MSHC_BASE 0x12240000
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#define EXYNOS5_SROMC_BASE 0x12250000
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#define EXYNOS5_UART_BASE 0x12C00000
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#define EXYNOS5_SPI1_BASE 0x12D30000
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#define EXYNOS5_I2C_BASE 0x12C60000
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#define EXYNOS5_SPI_BASE 0x12D20000
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#define EXYNOS5_SPI_ISP_BASE 0x131A0000
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#define EXYNOS5_I2S_BASE 0x12D60000
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#define EXYNOS5_GPIO_PART3_BASE 0x13400000 /* E00..H17 */
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#define EXYNOS5_FIMD_BASE 0x14400000
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#define EXYNOS5_DISP1_CTRL_BASE 0x14420000
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#define EXYNOS5_MIPI_DSI1_BASE 0x14500000
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#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
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/* Compatibility defines */
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#define EXYNOS_POWER_BASE EXYNOS5_POWER_BASE
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/* Marker values stored at the bottom of IRAM stack by SPL */
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#define EXYNOS5_SPL_MARKER 0xb004f1a9 /* hexspeak word: bootflag */
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/* Distance between each Trust Zone PC register set */
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#define TZPC_BASE_OFFSET 0x10000
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2013-08-06 02:18:44 +02:00
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/* TZPC : Register Offsets */
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#define TZPC0_BASE 0x10100000
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#define TZPC1_BASE 0x10110000
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#define TZPC2_BASE 0x10120000
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#define TZPC3_BASE 0x10130000
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#define TZPC4_BASE 0x10140000
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#define TZPC5_BASE 0x10150000
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#define TZPC6_BASE 0x10160000
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#define TZPC7_BASE 0x10170000
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#define TZPC8_BASE 0x10180000
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#define TZPC9_BASE 0x10190000
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#define TZPC10_BASE 0x100E0000
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#define TZPC11_BASE 0x100F0000
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/*
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* TZPC Register Value :
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* R0SIZE: 0x0 : Size of secured ram
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*/
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#define R0SIZE 0x0
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/*
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* TZPC Decode Protection Register Value :
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* DECPROTXSET: 0xFF : Set Decode region to non-secure
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*/
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#define DECPROTXSET 0xFF
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2012-11-27 19:36:06 +01:00
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ARM: remove code that is IMHO a dangerous design
OK, this is tl;dr. But I need to write this in hopes we make
sure we don't put code like this into coreboot. Ever.
Our excuse in this case is that it was imported, not obviously wrong,
and easily changed. It made sense to get it in, make it work, then
do a cleanup pass, because changing everything up front is almost
impossible to debug.
The exynos code has bunch of base register values, e.g.
These are base addresses of things that look like a memory-mapped
struct. To get these to a pointer, they created the following macro,
which creates an inline function.
static inline unsigned int samsung_get_base_##device(void) \
{ \
return cpu_is_exynos5() ? EXYNOS5_##base : 0; \
}
And then invoke it 31 times in a .h file, e.g.:
SAMSUNG_BASE(clock, CLOCK_BASE)
to create 31 functions.
And then use it:
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing.
I have a long list of what's wrong, and I may leave some things out,
but here goes:
1. the "function" can return a NULL if we're not on exynos5. Most uses of the code
don't check the return value.
2. And why would this function be running, if we're not on an exynos5? Why compile it in?
3. Note the cast everywhere a samsung_get_base_xxx is used.
The function returns an untyped variable, requiring the *user* to get two
things right: the cast, and the function invocation. One can replace that _clock(); with
_power(); in the code above, and they will be referencing the wrong registers, and
they'll never get an error!
We have a C compiler; use it to type data.
4. You're generating 31 functions using cpp each and every time the file is included.
The C compiler has to parse these each time. It's not at all like a simple cpp
macro which is only generated on use.
5. You can't tags or etags this code
6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic.
That's only a partial list.
So what's the right way to do it? Just make typed constants, viz:
Or, since I expect people will want the lower case function syntax, I've left
it that way:
Now we've got something that is efficient, and we don't even need to protect with
any more.
Hence this change. We've got something that is type checked, does not require users to
cast on each use, will catch simple programming errors, can be analyzed with standard tools,
and builds faster.
So if we make a mistake:
struct exynos5_clock *clk =
samsung_get_base_adc();
We'll see it:
src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk':
src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror]
which we would not have seen before.
As a minor benefit, it shaves most of a second off the compilation.
Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2582
Tested-by: build bot (Jenkins)
2013-03-04 18:46:31 +01:00
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#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE)
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#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE)
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#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE)
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#define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE)
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#define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE)
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#define samsung_get_base_fimd() ((struct exynos5_fimd *)EXYNOS5_FIMD_BASE)
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#define samsung_get_base_pro_id() ((struct exynos5_pro_id *)EXYNOS5_PRO_ID)
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#define samsung_get_base_mmc() ((struct exynos5_mmc *)EXYNOS5_MMC_BASE)
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#define samsung_get_base_mshci() ((struct exynos5_mshci *)EXYNOS5_MSHC_BASE)
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#define samsung_get_base_modem() ((struct exynos5_modem *)EXYNOS5_MODEM_BASE)
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#define samsung_get_base_sromc() ((struct exynos5_sromc *)EXYNOS5_SROMC_BASE)
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#define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET)
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#define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE)
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#define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE)
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#define samsung_get_base_usb_phy() ((struct exynos5_usb_phy *)EXYNOS5_USBPHY_BASE)
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#define samsung_get_base_usb_otg() ((struct exynos5_usb_otg *)EXYNOS5_USBOTG_BASE)
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#define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE)
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#define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE)
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#define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE)
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#define samsung_get_base_spi1() ((struct exynos5_spi1 *)EXYNOS5_SPI1_BASE)
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#define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE)
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#define samsung_get_base_spi() ((struct exynos5_spi *)EXYNOS5_SPI_BASE)
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#define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE)
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2012-11-27 19:36:06 +01:00
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#define EXYNOS5_SPI_NUM_CONTROLLERS 5
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#define EXYNOS_I2C_MAX_CONTROLLERS 8
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2013-03-29 03:04:58 +01:00
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void exynos5250_config_l2_cache(void);
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2013-04-18 23:21:15 +02:00
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extern struct tmu_info exynos5250_tmu_info;
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2013-06-20 00:54:19 +02:00
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/* TODO clean up defines. */
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#define FB_SIZE_KB 4096
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#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
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#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
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2013-08-06 02:18:44 +02:00
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struct exynos_tzpc {
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u32 r0size;
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u8 res1[0x7FC];
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u32 decprot0stat;
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u32 decprot0set;
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u32 decprot0clr;
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u32 decprot1stat;
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u32 decprot1set;
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u32 decprot1clr;
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u32 decprot2stat;
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u32 decprot2set;
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u32 decprot2clr;
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u32 decprot3stat;
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u32 decprot3set;
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u32 decprot3clr;
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u8 res2[0x7B0];
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u32 periphid0;
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u32 periphid1;
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u32 periphid2;
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u32 periphid3;
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u32 pcellid0;
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u32 pcellid1;
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u32 pcellid2;
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u32 pcellid3;
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};
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2013-06-20 00:54:19 +02:00
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static inline u32 get_fb_base_kb(void)
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{
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return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
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}
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2012-11-27 19:36:06 +01:00
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#endif /* _EXYNOS5250_CPU_H */
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