2007-04-22 21:08:13 +02:00
|
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|
/*
|
2008-01-18 11:35:56 +01:00
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* This file is part of the coreboot project.
|
2007-04-22 21:08:13 +02:00
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*
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* It was originally based on the Linux kernel (drivers/pci/pci.c).
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*
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* Modifications are:
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* Copyright (C) 2003-2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
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* Copyright (C) 2005-2006 Tyan
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* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
|
2009-04-21 22:14:31 +02:00
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* Copyright (C) 2005-2009 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
|
PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-05-13 05:46:31 +02:00
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
2007-04-22 21:08:13 +02:00
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*/
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|
2003-04-22 21:02:15 +02:00
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/*
|
2009-07-02 20:56:24 +02:00
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* PCI Bus Services, see include/linux/pci.h for further explanation.
|
2003-04-22 21:02:15 +02:00
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*
|
2009-07-02 20:56:24 +02:00
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* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
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* David Mosberger-Tang
|
2003-04-22 21:02:15 +02:00
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*
|
2009-07-02 20:56:24 +02:00
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* Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
|
2003-04-22 21:02:15 +02:00
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*/
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2014-06-20 13:19:06 +02:00
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <bootmode.h>
|
2003-04-22 21:02:15 +02:00
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#include <console/console.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
|
2014-06-20 13:19:06 +02:00
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#include <delay.h>
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#include <device/cardbus.h>
|
2003-04-24 08:25:08 +02:00
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
|
2005-07-08 04:49:49 +02:00
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#include <device/pcix.h>
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|
|
#include <device/pciexp.h>
|
2014-06-20 13:19:06 +02:00
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|
|
#include <device/hypertransport.h>
|
2009-07-21 23:36:41 +02:00
|
|
|
#include <pc80/i8259.h>
|
2014-06-20 13:19:06 +02:00
|
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|
#include <kconfig.h>
|
2012-03-31 02:10:49 +02:00
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|
#include <vendorcode/google/chromeos/chromeos.h>
|
2004-10-14 23:25:53 +02:00
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|
2009-07-02 20:56:24 +02:00
|
|
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u8 pci_moving_config8(struct device *dev, unsigned int reg)
|
2004-10-14 23:25:53 +02:00
|
|
|
{
|
2009-07-02 20:56:24 +02:00
|
|
|
u8 value, ones, zeroes;
|
2010-11-05 00:23:47 +01:00
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|
2004-10-14 23:25:53 +02:00
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|
value = pci_read_config8(dev, reg);
|
2009-05-12 00:24:53 +02:00
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|
2004-10-14 23:25:53 +02:00
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pci_write_config8(dev, reg, 0xff);
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|
ones = pci_read_config8(dev, reg);
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|
pci_write_config8(dev, reg, 0x00);
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|
zeroes = pci_read_config8(dev, reg);
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|
pci_write_config8(dev, reg, value);
|
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|
return ones ^ zeroes;
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|
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|
}
|
2004-12-23 22:48:01 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
u16 pci_moving_config16(struct device *dev, unsigned int reg)
|
2004-10-14 23:25:53 +02:00
|
|
|
{
|
2009-07-02 20:56:24 +02:00
|
|
|
u16 value, ones, zeroes;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2004-10-14 23:25:53 +02:00
|
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|
value = pci_read_config16(dev, reg);
|
2009-05-12 00:24:53 +02:00
|
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|
|
2004-10-14 23:25:53 +02:00
|
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|
pci_write_config16(dev, reg, 0xffff);
|
|
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|
ones = pci_read_config16(dev, reg);
|
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|
|
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|
pci_write_config16(dev, reg, 0x0000);
|
|
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|
zeroes = pci_read_config16(dev, reg);
|
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|
pci_write_config16(dev, reg, value);
|
|
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|
return ones ^ zeroes;
|
|
|
|
}
|
2004-12-27 05:25:41 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
u32 pci_moving_config32(struct device *dev, unsigned int reg)
|
2004-10-14 23:25:53 +02:00
|
|
|
{
|
2009-07-02 20:56:24 +02:00
|
|
|
u32 value, ones, zeroes;
|
2010-11-05 00:23:47 +01:00
|
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|
2004-10-14 23:25:53 +02:00
|
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|
value = pci_read_config32(dev, reg);
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2004-10-14 23:25:53 +02:00
|
|
|
pci_write_config32(dev, reg, 0xffffffff);
|
|
|
|
ones = pci_read_config32(dev, reg);
|
|
|
|
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|
|
|
pci_write_config32(dev, reg, 0x00000000);
|
|
|
|
zeroes = pci_read_config32(dev, reg);
|
|
|
|
|
|
|
|
pci_write_config32(dev, reg, value);
|
|
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|
|
|
return ones ^ zeroes;
|
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/**
|
|
|
|
* Given a device, a capability type, and a last position, return the next
|
|
|
|
* matching capability. Always start at the head of the list.
|
|
|
|
*
|
|
|
|
* @param dev Pointer to the device structure.
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
|
2009-07-02 20:56:24 +02:00
|
|
|
* @param last Location of the PCI capability register to start from.
|
2010-10-17 21:01:48 +02:00
|
|
|
* @return The next matching capability.
|
2009-07-02 20:56:24 +02:00
|
|
|
*/
|
|
|
|
unsigned pci_find_next_capability(struct device *dev, unsigned cap,
|
|
|
|
unsigned last)
|
2004-10-14 23:25:53 +02:00
|
|
|
{
|
2009-07-21 23:36:41 +02:00
|
|
|
unsigned pos = 0;
|
2010-11-05 00:23:47 +01:00
|
|
|
u16 status;
|
2005-07-08 04:49:49 +02:00
|
|
|
unsigned reps = 48;
|
2009-07-21 23:36:41 +02:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
status = pci_read_config16(dev, PCI_STATUS);
|
2010-11-05 00:23:47 +01:00
|
|
|
if (!(status & PCI_STATUS_CAP_LIST))
|
2005-07-08 04:49:49 +02:00
|
|
|
return 0;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
switch (dev->hdr_type & 0x7f) {
|
2004-10-14 23:25:53 +02:00
|
|
|
case PCI_HEADER_TYPE_NORMAL:
|
|
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
|
|
|
pos = PCI_CAPABILITY_LIST;
|
|
|
|
break;
|
2005-07-08 04:49:49 +02:00
|
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
|
|
|
pos = PCI_CB_CAPABILITY_LIST;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
pos = pci_read_config8(dev, pos);
|
2010-11-05 00:23:47 +01:00
|
|
|
while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
|
2004-10-14 23:25:53 +02:00
|
|
|
int this_cap;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
pos &= ~3;
|
2004-10-14 23:25:53 +02:00
|
|
|
this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
|
|
|
|
this_cap, pos);
|
|
|
|
if (this_cap == 0xff)
|
2005-07-08 04:49:49 +02:00
|
|
|
break;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
if (!last && (this_cap == cap))
|
2004-10-14 23:25:53 +02:00
|
|
|
return pos;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
if (last == pos)
|
2005-07-08 04:49:49 +02:00
|
|
|
last = 0;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/**
|
|
|
|
* Given a device, and a capability type, return the next matching
|
|
|
|
* capability. Always start at the head of the list.
|
|
|
|
*
|
|
|
|
* @param dev Pointer to the device structure.
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
|
|
|
|
* @return The next matching capability.
|
2009-07-02 20:56:24 +02:00
|
|
|
*/
|
2005-07-08 04:49:49 +02:00
|
|
|
unsigned pci_find_capability(device_t dev, unsigned cap)
|
|
|
|
{
|
|
|
|
return pci_find_next_capability(dev, cap, 0);
|
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/**
|
|
|
|
* Given a device and register, read the size of the BAR for that register.
|
|
|
|
*
|
|
|
|
* @param dev Pointer to the device structure.
|
|
|
|
* @param index Address of the PCI configuration register.
|
2010-10-17 21:01:48 +02:00
|
|
|
* @return TODO
|
2003-04-22 21:02:15 +02:00
|
|
|
*/
|
2004-10-14 23:25:53 +02:00
|
|
|
struct resource *pci_get_resource(struct device *dev, unsigned long index)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
2004-03-11 16:01:31 +01:00
|
|
|
struct resource *resource;
|
2004-10-14 23:25:53 +02:00
|
|
|
unsigned long value, attr;
|
2009-07-02 20:56:24 +02:00
|
|
|
resource_t moving, limit;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Initialize the resources to nothing. */
|
2004-10-14 23:25:53 +02:00
|
|
|
resource = new_resource(dev, index);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Get the initial value. */
|
2004-10-14 23:25:53 +02:00
|
|
|
value = pci_read_config32(dev, index);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* See which bits move. */
|
2004-10-14 23:25:53 +02:00
|
|
|
moving = pci_moving_config32(dev, index);
|
2004-12-23 22:48:01 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Initialize attr to the bits that do not move. */
|
2004-10-14 23:25:53 +02:00
|
|
|
attr = value & ~moving;
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* If it is a 64bit resource look at the high half as well. */
|
2004-10-14 23:25:53 +02:00
|
|
|
if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
|
2009-07-02 20:56:24 +02:00
|
|
|
((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
|
|
|
|
PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
|
|
|
|
/* Find the high bits that move. */
|
|
|
|
moving |=
|
|
|
|
((resource_t) pci_moving_config32(dev, index + 4)) << 32;
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-05-12 00:24:53 +02:00
|
|
|
/* Find the resource constraints.
|
2004-10-14 23:25:53 +02:00
|
|
|
* Start by finding the bits that move. From there:
|
|
|
|
* - Size is the least significant bit of the bits that move.
|
|
|
|
* - Limit is all of the bits that move plus all of the lower bits.
|
2009-07-02 20:56:24 +02:00
|
|
|
* See PCI Spec 6.2.5.1.
|
2003-04-22 21:02:15 +02:00
|
|
|
*/
|
2004-10-14 23:25:53 +02:00
|
|
|
limit = 0;
|
|
|
|
if (moving) {
|
|
|
|
resource->size = 1;
|
|
|
|
resource->align = resource->gran = 0;
|
2009-07-02 20:56:24 +02:00
|
|
|
while (!(moving & resource->size)) {
|
2004-10-14 23:25:53 +02:00
|
|
|
resource->size <<= 1;
|
|
|
|
resource->align += 1;
|
2009-07-02 20:56:24 +02:00
|
|
|
resource->gran += 1;
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
|
|
|
resource->limit = limit = moving | (resource->size - 1);
|
|
|
|
}
|
2009-07-02 20:56:24 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Some broken hardware has read-only registers that do not
|
2004-10-14 23:25:53 +02:00
|
|
|
* really size correctly.
|
2010-11-05 00:23:47 +01:00
|
|
|
*
|
|
|
|
* Example: the Acer M7229 has BARs 1-4 normally read-only,
|
2003-04-22 21:02:15 +02:00
|
|
|
* so BAR1 at offset 0x10 reads 0x1f1. If you size that register
|
2010-11-05 00:23:47 +01:00
|
|
|
* by writing 0xffffffff to it, it will read back as 0x1f1 -- which
|
|
|
|
* is a violation of the spec.
|
|
|
|
*
|
|
|
|
* We catch this case and ignore it by observing which bits move.
|
|
|
|
*
|
|
|
|
* This also catches the common case of unimplemented registers
|
2004-10-14 23:25:53 +02:00
|
|
|
* that always read back as 0.
|
2003-04-22 21:02:15 +02:00
|
|
|
*/
|
2004-10-14 23:25:53 +02:00
|
|
|
if (moving == 0) {
|
|
|
|
if (value != 0) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
|
|
|
|
"read-only ignoring it\n",
|
|
|
|
dev_path(dev), index, value);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
resource->flags = 0;
|
2009-07-02 20:56:24 +02:00
|
|
|
} else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
/* An I/O mapped base address. */
|
2004-10-14 23:25:53 +02:00
|
|
|
attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
|
2004-03-11 16:01:31 +01:00
|
|
|
resource->flags |= IORESOURCE_IO;
|
2009-07-02 20:56:24 +02:00
|
|
|
/* I don't want to deal with 32bit I/O resources. */
|
2003-04-22 21:02:15 +02:00
|
|
|
resource->limit = 0xffff;
|
2009-07-02 20:56:24 +02:00
|
|
|
} else {
|
|
|
|
/* A Memory mapped base address. */
|
2004-10-14 23:25:53 +02:00
|
|
|
attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
2004-03-11 16:01:31 +01:00
|
|
|
resource->flags |= IORESOURCE_MEM;
|
2010-11-05 00:23:47 +01:00
|
|
|
if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
|
2003-04-22 21:02:15 +02:00
|
|
|
resource->flags |= IORESOURCE_PREFETCH;
|
2004-10-14 23:25:53 +02:00
|
|
|
attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
|
|
|
|
if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
|
2009-07-02 20:56:24 +02:00
|
|
|
/* 32bit limit. */
|
2003-04-22 21:02:15 +02:00
|
|
|
resource->limit = 0xffffffffUL;
|
2009-07-02 20:56:24 +02:00
|
|
|
} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
|
|
|
|
/* 1MB limit. */
|
2003-04-22 21:02:15 +02:00
|
|
|
resource->limit = 0x000fffffUL;
|
2009-07-02 20:56:24 +02:00
|
|
|
} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
|
|
|
|
/* 64bit limit. */
|
2004-10-14 23:25:53 +02:00
|
|
|
resource->limit = 0xffffffffffffffffULL;
|
2003-04-22 21:02:15 +02:00
|
|
|
resource->flags |= IORESOURCE_PCI64;
|
2009-07-02 20:56:24 +02:00
|
|
|
} else {
|
|
|
|
/* Invalid value. */
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
|
|
|
|
printk(BIOS_ERR, " on dev %s at index %02lx\n",
|
2009-07-02 20:56:24 +02:00
|
|
|
dev_path(dev), index);
|
2003-04-22 21:02:15 +02:00
|
|
|
resource->flags = 0;
|
|
|
|
}
|
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Don't let the limit exceed which bits can move. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->limit > limit)
|
2004-10-14 23:25:53 +02:00
|
|
|
resource->limit = limit;
|
|
|
|
|
2004-03-11 16:01:31 +01:00
|
|
|
return resource;
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/**
|
|
|
|
* Given a device and an index, read the size of the BAR for that register.
|
|
|
|
*
|
|
|
|
* @param dev Pointer to the device structure.
|
|
|
|
* @param index Address of the PCI configuration register.
|
|
|
|
*/
|
2004-12-27 05:25:41 +01:00
|
|
|
static void pci_get_rom_resource(struct device *dev, unsigned long index)
|
2004-12-23 22:48:01 +01:00
|
|
|
{
|
|
|
|
struct resource *resource;
|
2004-12-27 05:25:41 +01:00
|
|
|
unsigned long value;
|
2009-07-02 20:56:24 +02:00
|
|
|
resource_t moving;
|
2004-12-23 22:48:01 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Initialize the resources to nothing. */
|
2004-12-23 22:48:01 +01:00
|
|
|
resource = new_resource(dev, index);
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Get the initial value. */
|
2004-12-23 22:48:01 +01:00
|
|
|
value = pci_read_config32(dev, index);
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* See which bits move. */
|
2004-12-23 22:48:01 +01:00
|
|
|
moving = pci_moving_config32(dev, index);
|
2009-07-02 20:56:24 +02:00
|
|
|
|
|
|
|
/* Clear the Enable bit. */
|
2004-12-27 05:25:41 +01:00
|
|
|
moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
|
2004-12-23 22:48:01 +01:00
|
|
|
|
2009-05-12 00:24:53 +02:00
|
|
|
/* Find the resource constraints.
|
2004-12-23 22:48:01 +01:00
|
|
|
* Start by finding the bits that move. From there:
|
|
|
|
* - Size is the least significant bit of the bits that move.
|
|
|
|
* - Limit is all of the bits that move plus all of the lower bits.
|
2009-07-02 20:56:24 +02:00
|
|
|
* See PCI Spec 6.2.5.1.
|
2004-12-23 22:48:01 +01:00
|
|
|
*/
|
|
|
|
if (moving) {
|
|
|
|
resource->size = 1;
|
|
|
|
resource->align = resource->gran = 0;
|
2004-12-27 05:25:41 +01:00
|
|
|
while (!(moving & resource->size)) {
|
2004-12-23 22:48:01 +01:00
|
|
|
resource->size <<= 1;
|
|
|
|
resource->align += 1;
|
2009-07-02 20:56:24 +02:00
|
|
|
resource->gran += 1;
|
2004-12-23 22:48:01 +01:00
|
|
|
}
|
2009-04-21 22:14:31 +02:00
|
|
|
resource->limit = moving | (resource->size - 1);
|
2009-07-02 20:56:24 +02:00
|
|
|
resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
|
|
|
|
} else {
|
2004-12-23 22:48:01 +01:00
|
|
|
if (value != 0) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
|
|
|
|
"read-only ignoring it\n",
|
|
|
|
dev_path(dev), index, value);
|
2004-12-23 22:48:01 +01:00
|
|
|
}
|
|
|
|
resource->flags = 0;
|
|
|
|
}
|
2005-07-08 04:49:49 +02:00
|
|
|
compact_resources(dev);
|
2004-12-27 05:25:41 +01:00
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/**
|
|
|
|
* Read the base address registers for a given device.
|
|
|
|
*
|
|
|
|
* @param dev Pointer to the dev structure.
|
|
|
|
* @param howmany How many registers to read (6 for device, 2 for bridge).
|
2004-12-27 05:25:41 +01:00
|
|
|
*/
|
2005-07-08 04:49:49 +02:00
|
|
|
static void pci_read_bases(struct device *dev, unsigned int howmany)
|
2004-12-27 05:25:41 +01:00
|
|
|
{
|
|
|
|
unsigned long index;
|
2004-12-23 22:48:01 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
for (index = PCI_BASE_ADDRESS_0;
|
|
|
|
(index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
|
2004-12-27 05:25:41 +01:00
|
|
|
struct resource *resource;
|
|
|
|
resource = pci_get_resource(dev, index);
|
2009-07-02 20:56:24 +02:00
|
|
|
index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
|
2004-12-27 05:25:41 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
compact_resources(dev);
|
2004-12-23 22:48:01 +01:00
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
static void pci_record_bridge_resource(struct device *dev, resource_t moving,
|
|
|
|
unsigned index, unsigned long type)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
2004-03-11 16:01:31 +01:00
|
|
|
struct resource *resource;
|
2010-11-05 00:23:47 +01:00
|
|
|
unsigned long gran;
|
|
|
|
resource_t step;
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
resource = NULL;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
if (!moving)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Initialize the constraints on the current bus. */
|
|
|
|
resource = new_resource(dev, index);
|
|
|
|
resource->size = 0;
|
|
|
|
gran = 0;
|
|
|
|
step = 1;
|
|
|
|
while ((moving & step) == 0) {
|
|
|
|
gran += 1;
|
|
|
|
step <<= 1;
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
resource->gran = gran;
|
|
|
|
resource->align = gran;
|
|
|
|
resource->limit = moving | (step - 1);
|
|
|
|
resource->flags = type | IORESOURCE_PCI_BRIDGE |
|
|
|
|
IORESOURCE_BRIDGE;
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2004-10-14 23:25:53 +02:00
|
|
|
static void pci_bridge_read_bases(struct device *dev)
|
|
|
|
{
|
|
|
|
resource_t moving_base, moving_limit, moving;
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* See if the bridge I/O resources are implemented. */
|
|
|
|
moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
|
|
|
|
moving_base |=
|
2010-10-17 21:01:48 +02:00
|
|
|
((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
|
2004-10-14 23:25:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
|
|
|
|
moving_limit |=
|
2010-10-17 21:01:48 +02:00
|
|
|
((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
|
2004-10-14 23:25:53 +02:00
|
|
|
|
|
|
|
moving = moving_base & moving_limit;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Initialize the I/O space constraints on the current bus. */
|
|
|
|
pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
|
2005-07-08 04:49:49 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* See if the bridge prefmem resources are implemented. */
|
|
|
|
moving_base =
|
2010-10-17 21:01:48 +02:00
|
|
|
((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
|
2009-07-02 20:56:24 +02:00
|
|
|
moving_base |=
|
2010-10-17 21:01:48 +02:00
|
|
|
((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
|
2004-10-14 23:25:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
moving_limit =
|
2010-10-17 21:01:48 +02:00
|
|
|
((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
|
2009-07-02 20:56:24 +02:00
|
|
|
moving_limit |=
|
2010-10-17 21:01:48 +02:00
|
|
|
((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2004-10-14 23:25:53 +02:00
|
|
|
moving = moving_base & moving_limit;
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Initialize the prefetchable memory constraints on the current bus. */
|
|
|
|
pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
|
|
|
|
IORESOURCE_MEM | IORESOURCE_PREFETCH);
|
2004-10-14 23:25:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* See if the bridge mem resources are implemented. */
|
|
|
|
moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
|
|
|
|
moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
|
2004-10-14 23:25:53 +02:00
|
|
|
|
|
|
|
moving = moving_base & moving_limit;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Initialize the memory resources on the current bus. */
|
|
|
|
pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
|
|
|
|
IORESOURCE_MEM);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2004-03-11 16:01:31 +01:00
|
|
|
compact_resources(dev);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2003-04-24 08:25:08 +02:00
|
|
|
void pci_dev_read_resources(struct device *dev)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
2005-07-08 04:49:49 +02:00
|
|
|
pci_read_bases(dev, 6);
|
|
|
|
pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2003-04-24 08:25:08 +02:00
|
|
|
void pci_bus_read_resources(struct device *dev)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
|
|
|
pci_bridge_read_bases(dev);
|
2005-07-08 04:49:49 +02:00
|
|
|
pci_read_bases(dev, 2);
|
|
|
|
pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
void pci_domain_read_resources(struct device *dev)
|
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
/* Initialize the system-wide I/O space constraints. */
|
|
|
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
|
|
|
res->limit = 0xffffUL;
|
|
|
|
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
|
|
|
IORESOURCE_ASSIGNED;
|
|
|
|
|
|
|
|
/* Initialize the system-wide memory resources constraints. */
|
|
|
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
|
|
|
res->limit = 0xffffffffULL;
|
|
|
|
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
|
|
|
IORESOURCE_ASSIGNED;
|
|
|
|
}
|
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
static void pci_set_resource(struct device *dev, struct resource *resource)
|
|
|
|
{
|
2004-10-14 23:25:53 +02:00
|
|
|
resource_t base, end;
|
2003-09-02 05:36:25 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Make certain the resource has actually been assigned a value. */
|
2004-03-11 16:01:31 +01:00
|
|
|
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
|
|
|
|
"assigned\n", dev_path(dev), resource->index,
|
|
|
|
resource_type(resource), resource->size);
|
2003-04-22 21:02:15 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-11-05 21:06:19 +01:00
|
|
|
/* If this resource is fixed don't worry about it. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_FIXED)
|
2009-11-05 21:06:19 +01:00
|
|
|
return;
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* If I have already stored this resource don't worry about it. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_STORED)
|
2004-03-11 16:01:31 +01:00
|
|
|
return;
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* If the resource is subtractive don't worry about it. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_SUBTRACTIVE)
|
2004-10-14 23:25:53 +02:00
|
|
|
return;
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Only handle PCI memory and I/O resources for now. */
|
|
|
|
if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
|
2003-04-22 21:02:15 +02:00
|
|
|
return;
|
2003-09-02 05:36:25 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Enable the resources in the command register. */
|
2004-10-14 23:25:53 +02:00
|
|
|
if (resource->size) {
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_MEM)
|
2004-10-14 23:25:53 +02:00
|
|
|
dev->command |= PCI_COMMAND_MEMORY;
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_IO)
|
2004-10-14 23:25:53 +02:00
|
|
|
dev->command |= PCI_COMMAND_IO;
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_PCI_BRIDGE)
|
2004-10-14 23:25:53 +02:00
|
|
|
dev->command |= PCI_COMMAND_MASTER;
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Get the base address. */
|
2003-04-22 21:02:15 +02:00
|
|
|
base = resource->base;
|
2004-03-11 16:01:31 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Get the end. */
|
2004-10-14 23:25:53 +02:00
|
|
|
end = resource_end(resource);
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Now store the resource. */
|
2004-03-11 16:01:31 +01:00
|
|
|
resource->flags |= IORESOURCE_STORED;
|
2009-07-02 20:56:24 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* PCI bridges have no enable bit. They are disabled if the base of
|
|
|
|
* the range is greater than the limit. If the size is zero, disable
|
2009-07-02 20:56:24 +02:00
|
|
|
* by setting the base = limit and end = limit - 2^gran.
|
|
|
|
*/
|
|
|
|
if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
|
|
|
|
base = resource->limit;
|
|
|
|
end = resource->limit - (1 << resource->gran);
|
|
|
|
resource->base = base;
|
|
|
|
}
|
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
|
2004-10-14 23:25:53 +02:00
|
|
|
unsigned long base_lo, base_hi;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Some chipsets allow us to set/clear the I/O bit
|
|
|
|
* (e.g. VIA 82C686A). So set it to be safe.
|
2004-10-14 22:54:17 +02:00
|
|
|
*/
|
2004-10-14 23:25:53 +02:00
|
|
|
base_lo = base & 0xffffffff;
|
|
|
|
base_hi = (base >> 32) & 0xffffffff;
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_IO)
|
2004-10-14 23:25:53 +02:00
|
|
|
base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
|
|
|
|
pci_write_config32(dev, resource->index, base_lo);
|
2010-11-05 00:23:47 +01:00
|
|
|
if (resource->flags & IORESOURCE_PCI64)
|
2004-10-14 23:25:53 +02:00
|
|
|
pci_write_config32(dev, resource->index + 4, base_hi);
|
2009-07-02 20:56:24 +02:00
|
|
|
} else if (resource->index == PCI_IO_BASE) {
|
|
|
|
/* Set the I/O ranges. */
|
|
|
|
pci_write_config8(dev, PCI_IO_BASE, base >> 8);
|
2004-10-14 23:25:53 +02:00
|
|
|
pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
|
2009-07-02 20:56:24 +02:00
|
|
|
pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
|
2004-10-14 23:25:53 +02:00
|
|
|
pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
|
2009-07-02 20:56:24 +02:00
|
|
|
} else if (resource->index == PCI_MEMORY_BASE) {
|
|
|
|
/* Set the memory range. */
|
2003-06-12 21:23:51 +02:00
|
|
|
pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
|
2004-10-14 23:25:53 +02:00
|
|
|
pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
|
2009-07-02 20:56:24 +02:00
|
|
|
} else if (resource->index == PCI_PREF_MEMORY_BASE) {
|
|
|
|
/* Set the prefetchable memory range. */
|
2004-10-14 23:25:53 +02:00
|
|
|
pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
|
|
|
|
pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
|
|
|
|
pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
|
|
|
|
pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
|
2009-07-02 20:56:24 +02:00
|
|
|
} else {
|
|
|
|
/* Don't let me think I stored the resource. */
|
2004-03-11 16:01:31 +01:00
|
|
|
resource->flags &= ~IORESOURCE_STORED;
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
|
2010-11-05 00:23:47 +01:00
|
|
|
resource->index);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2004-10-14 23:25:53 +02:00
|
|
|
report_resource_stored(dev, resource, "");
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2003-04-24 08:25:08 +02:00
|
|
|
void pci_dev_set_resources(struct device *dev)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
2010-05-21 16:33:48 +02:00
|
|
|
struct resource *res;
|
2010-06-10 00:41:35 +02:00
|
|
|
struct bus *bus;
|
2009-07-02 20:56:24 +02:00
|
|
|
u8 line;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
for (res = dev->resource_list; res; res = res->next)
|
2010-05-21 16:33:48 +02:00
|
|
|
pci_set_resource(dev, res);
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2010-06-10 00:41:35 +02:00
|
|
|
for (bus = dev->link_list; bus; bus = bus->next) {
|
2010-11-05 00:23:47 +01:00
|
|
|
if (bus->children)
|
2003-09-02 05:36:25 +02:00
|
|
|
assign_resources(bus);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Set a default latency timer. */
|
2003-06-12 21:23:51 +02:00
|
|
|
pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Set a default secondary latency timer. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
|
2003-06-12 21:23:51 +02:00
|
|
|
pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Zero the IRQ settings. */
|
2003-06-12 21:23:51 +02:00
|
|
|
line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
|
2010-11-05 00:23:47 +01:00
|
|
|
if (line)
|
2003-06-12 21:23:51 +02:00
|
|
|
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Set the cache line size, so far 64 bytes is good for everyone. */
|
2003-06-12 21:23:51 +02:00
|
|
|
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
|
2003-09-02 05:36:25 +02:00
|
|
|
void pci_dev_enable_resources(struct device *dev)
|
|
|
|
{
|
2004-11-18 23:38:08 +01:00
|
|
|
const struct pci_operations *ops;
|
2009-07-02 20:56:24 +02:00
|
|
|
u16 command;
|
2004-10-14 23:25:53 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* Set the subsystem vendor and device ID for mainboard devices. */
|
2004-10-14 23:25:53 +02:00
|
|
|
ops = ops_pci(dev);
|
2004-10-21 12:44:08 +02:00
|
|
|
if (dev->on_mainboard && ops && ops->set_subsystem) {
|
2013-08-09 16:55:10 +02:00
|
|
|
if (CONFIG_SUBSYSTEM_VENDOR_ID)
|
|
|
|
dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID;
|
|
|
|
if (CONFIG_SUBSYSTEM_DEVICE_ID)
|
|
|
|
dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID;
|
2011-03-01 20:58:47 +01:00
|
|
|
printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
|
|
|
|
dev_path(dev), dev->subsystem_vendor,
|
|
|
|
dev->subsystem_device);
|
|
|
|
ops->set_subsystem(dev, dev->subsystem_vendor,
|
|
|
|
dev->subsystem_device);
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
2003-09-02 05:36:25 +02:00
|
|
|
command = pci_read_config16(dev, PCI_COMMAND);
|
|
|
|
command |= dev->command;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* v3 has
|
|
|
|
* command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
|
|
|
|
*/
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
|
2003-09-02 05:36:25 +02:00
|
|
|
pci_write_config16(dev, PCI_COMMAND, command);
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_bus_enable_resources(struct device *dev)
|
|
|
|
{
|
2009-07-02 20:56:24 +02:00
|
|
|
u16 ctrl;
|
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Enable I/O in command register if there is VGA card
|
2009-07-02 20:56:24 +02:00
|
|
|
* connected with (even it does not claim I/O resource).
|
|
|
|
*/
|
2010-06-10 00:41:35 +02:00
|
|
|
if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
|
2005-01-11 23:48:54 +01:00
|
|
|
dev->command |= PCI_COMMAND_IO;
|
2003-09-02 05:36:25 +02:00
|
|
|
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
|
2010-06-10 00:41:35 +02:00
|
|
|
ctrl |= dev->link_list->bridge_ctrl;
|
2010-11-05 00:23:47 +01:00
|
|
|
ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
|
2003-09-02 05:36:25 +02:00
|
|
|
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
|
|
|
|
|
|
|
|
pci_dev_enable_resources(dev);
|
|
|
|
}
|
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
void pci_bus_reset(struct bus *bus)
|
|
|
|
{
|
2010-11-05 00:23:47 +01:00
|
|
|
u16 ctl;
|
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
|
|
|
|
ctl |= PCI_BRIDGE_CTL_BUS_RESET;
|
|
|
|
pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
|
|
|
|
mdelay(10);
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
|
|
|
|
pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
|
|
|
|
delay(1);
|
|
|
|
}
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
|
2004-10-14 23:25:53 +02:00
|
|
|
{
|
2009-05-12 00:24:53 +02:00
|
|
|
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
2009-07-02 20:56:24 +02:00
|
|
|
((device & 0xffff) << 16) | (vendor & 0xffff));
|
2004-10-14 23:25:53 +02:00
|
|
|
}
|
|
|
|
|
2013-12-20 17:47:19 +01:00
|
|
|
#if CONFIG_VGA_ROM_RUN
|
2014-05-01 15:31:34 +02:00
|
|
|
static int should_run_oprom(struct device *dev)
|
|
|
|
{
|
|
|
|
static int should_run = -1;
|
2005-01-11 00:16:22 +01:00
|
|
|
|
2014-05-01 15:31:34 +02:00
|
|
|
if (should_run >= 0)
|
|
|
|
return should_run;
|
2007-04-06 20:34:39 +02:00
|
|
|
|
2013-12-21 23:22:49 +01:00
|
|
|
/* Don't run VGA option ROMs, unless we have to print
|
2012-03-31 02:10:49 +02:00
|
|
|
* something on the screen before the kernel is loaded.
|
|
|
|
*/
|
2013-12-21 23:22:49 +01:00
|
|
|
should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) ||
|
|
|
|
developer_mode_enabled() || recovery_mode_enabled();
|
2014-05-01 15:31:34 +02:00
|
|
|
|
2013-12-21 23:22:49 +01:00
|
|
|
#if CONFIG_CHROMEOS
|
|
|
|
if (!should_run)
|
|
|
|
should_run = vboot_wants_oprom();
|
|
|
|
#endif
|
|
|
|
if (!should_run)
|
|
|
|
printk(BIOS_DEBUG, "Not running VGA Option ROM\n");
|
2014-05-01 15:31:34 +02:00
|
|
|
return should_run;
|
|
|
|
}
|
2012-03-31 02:10:49 +02:00
|
|
|
|
2014-05-01 15:31:34 +02:00
|
|
|
static int should_load_oprom(struct device *dev)
|
|
|
|
{
|
2011-09-23 19:33:58 +02:00
|
|
|
/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
|
|
|
|
* ROMs when coming out of an S3 resume.
|
|
|
|
*/
|
2014-06-20 05:21:01 +02:00
|
|
|
if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() &&
|
2011-09-23 19:33:58 +02:00
|
|
|
((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
|
2014-05-01 15:31:34 +02:00
|
|
|
return 0;
|
|
|
|
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
|
|
|
|
return 1;
|
|
|
|
if (should_run_oprom(dev))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_VGA_ROM_RUN */
|
|
|
|
|
|
|
|
/** Default handler: only runs the relevant PCI BIOS. */
|
|
|
|
void pci_dev_init(struct device *dev)
|
|
|
|
{
|
|
|
|
#if CONFIG_VGA_ROM_RUN
|
|
|
|
struct rom_header *rom, *ram;
|
|
|
|
|
|
|
|
/* Only execute VGA ROMs. */
|
|
|
|
if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!should_load_oprom(dev))
|
|
|
|
return;
|
2013-03-28 21:59:19 +01:00
|
|
|
|
|
|
|
rom = pci_rom_probe(dev);
|
|
|
|
if (rom == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
ram = pci_rom_load(dev, rom);
|
|
|
|
if (ram == NULL)
|
|
|
|
return;
|
|
|
|
|
2014-05-01 15:31:34 +02:00
|
|
|
if (!should_run_oprom(dev))
|
|
|
|
return;
|
|
|
|
|
2008-08-01 13:25:41 +02:00
|
|
|
run_bios(dev, (unsigned long)ram);
|
2013-11-28 15:44:51 +01:00
|
|
|
gfx_set_init_done(1);
|
|
|
|
printk(BIOS_DEBUG, "VGA Option ROM was run\n");
|
2013-12-20 17:47:19 +01:00
|
|
|
#endif /* CONFIG_VGA_ROM_RUN */
|
2005-07-08 04:49:49 +02:00
|
|
|
}
|
2005-01-11 00:16:22 +01:00
|
|
|
|
2004-03-23 22:28:05 +01:00
|
|
|
/** Default device operation for PCI devices */
|
2004-11-18 23:38:08 +01:00
|
|
|
static struct pci_operations pci_dev_ops_pci = {
|
2004-10-14 23:25:53 +02:00
|
|
|
.set_subsystem = pci_dev_set_subsystem,
|
|
|
|
};
|
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
struct device_operations default_pci_ops_dev = {
|
2010-11-05 00:23:47 +01:00
|
|
|
.read_resources = pci_dev_read_resources,
|
|
|
|
.set_resources = pci_dev_set_resources,
|
2003-09-02 05:36:25 +02:00
|
|
|
.enable_resources = pci_dev_enable_resources,
|
2010-11-05 00:23:47 +01:00
|
|
|
.init = pci_dev_init,
|
|
|
|
.scan_bus = 0,
|
|
|
|
.enable = 0,
|
|
|
|
.ops_pci = &pci_dev_ops_pci,
|
2003-04-22 21:02:15 +02:00
|
|
|
};
|
2004-03-23 22:28:05 +01:00
|
|
|
|
|
|
|
/** Default device operations for PCI bridges */
|
2004-11-18 23:38:08 +01:00
|
|
|
static struct pci_operations pci_bus_ops_pci = {
|
2004-10-14 23:25:53 +02:00
|
|
|
.set_subsystem = 0,
|
|
|
|
};
|
2005-01-11 00:16:22 +01:00
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
struct device_operations default_pci_ops_bus = {
|
2010-11-05 00:23:47 +01:00
|
|
|
.read_resources = pci_bus_read_resources,
|
|
|
|
.set_resources = pci_dev_set_resources,
|
2003-09-02 05:36:25 +02:00
|
|
|
.enable_resources = pci_bus_enable_resources,
|
2010-11-05 00:23:47 +01:00
|
|
|
.init = 0,
|
|
|
|
.scan_bus = pci_scan_bridge,
|
|
|
|
.enable = 0,
|
|
|
|
.reset_bus = pci_bus_reset,
|
|
|
|
.ops_pci = &pci_bus_ops_pci,
|
2003-04-22 21:02:15 +02:00
|
|
|
};
|
2004-03-23 22:28:05 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Detect the type of downstream bridge.
|
2005-07-08 04:49:49 +02:00
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* This function is a heuristic to detect which type of bus is downstream
|
|
|
|
* of a PCI-to-PCI bridge. This functions by looking for various capability
|
|
|
|
* blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
|
|
|
|
* Hypertransport all seem to have appropriate capabilities.
|
2009-05-12 00:24:53 +02:00
|
|
|
*
|
2010-11-05 00:23:47 +01:00
|
|
|
* When only a PCI-Express capability is found the type is examined to see
|
|
|
|
* which type of bridge we have.
|
2005-07-08 04:49:49 +02:00
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* @param dev Pointer to the device structure of the bridge.
|
|
|
|
* @return Appropriate bridge operations.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
|
|
|
static struct device_operations *get_pci_bridge_ops(device_t dev)
|
|
|
|
{
|
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-05 15:29:32 +02:00
|
|
|
#if CONFIG_PCIX_PLUGIN_SUPPORT
|
2012-11-30 01:28:21 +01:00
|
|
|
unsigned int pcixpos;
|
|
|
|
pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (pcixpos) {
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
|
2005-07-08 04:49:49 +02:00
|
|
|
return &default_pcix_ops_bus;
|
|
|
|
}
|
|
|
|
#endif
|
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-05 15:29:32 +02:00
|
|
|
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
|
2012-11-30 01:28:21 +01:00
|
|
|
unsigned int htpos = 0;
|
|
|
|
while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) {
|
2010-11-05 00:23:47 +01:00
|
|
|
u16 flags;
|
2012-11-30 01:28:21 +01:00
|
|
|
flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS);
|
2005-07-08 04:49:49 +02:00
|
|
|
if ((flags >> 13) == 1) {
|
|
|
|
/* Host or Secondary Interface */
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_DEBUG, "%s subordinate bus HT\n",
|
|
|
|
dev_path(dev));
|
2005-07-08 04:49:49 +02:00
|
|
|
return &default_ht_ops_bus;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-05 15:29:32 +02:00
|
|
|
#if CONFIG_PCIEXP_PLUGIN_SUPPORT
|
2012-11-30 01:28:21 +01:00
|
|
|
unsigned int pciexpos;
|
|
|
|
pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
|
|
|
|
if (pciexpos) {
|
2010-11-05 00:23:47 +01:00
|
|
|
u16 flags;
|
2012-11-30 01:28:21 +01:00
|
|
|
flags = pci_read_config16(dev, pciexpos + PCI_EXP_FLAGS);
|
2009-07-02 20:56:24 +02:00
|
|
|
switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
|
2005-07-08 04:49:49 +02:00
|
|
|
case PCI_EXP_TYPE_ROOT_PORT:
|
|
|
|
case PCI_EXP_TYPE_UPSTREAM:
|
|
|
|
case PCI_EXP_TYPE_DOWNSTREAM:
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
|
2010-11-05 00:23:47 +01:00
|
|
|
dev_path(dev));
|
2005-07-08 04:49:49 +02:00
|
|
|
return &default_pciexp_ops_bus;
|
|
|
|
case PCI_EXP_TYPE_PCI_BRIDGE:
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_DEBUG, "%s subordinate PCI\n",
|
|
|
|
dev_path(dev));
|
2005-07-08 04:49:49 +02:00
|
|
|
return &default_pci_ops_bus;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
return &default_pci_ops_bus;
|
|
|
|
}
|
|
|
|
|
2012-04-24 21:53:19 +02:00
|
|
|
/**
|
|
|
|
* Check if a device id matches a PCI driver entry.
|
|
|
|
*
|
|
|
|
* The driver entry can either point at a zero terminated array of acceptable
|
|
|
|
* device IDs, or include a single device ID.
|
|
|
|
*
|
2015-01-07 05:02:52 +01:00
|
|
|
* @param driver pointer to the PCI driver entry being checked
|
|
|
|
* @param device_id PCI device ID of the device being matched
|
2012-04-24 21:53:19 +02:00
|
|
|
*/
|
|
|
|
static int device_id_match(struct pci_driver *driver, unsigned short device_id)
|
|
|
|
{
|
|
|
|
if (driver->devices) {
|
|
|
|
unsigned short check_id;
|
|
|
|
const unsigned short *device_list = driver->devices;
|
|
|
|
while ((check_id = *device_list++) != 0)
|
|
|
|
if (check_id == device_id)
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (driver->device == device_id);
|
|
|
|
}
|
|
|
|
|
2004-03-23 22:28:05 +01:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Set up PCI device operation.
|
|
|
|
*
|
|
|
|
* Check if it already has a driver. If not, use find_device_operations(),
|
|
|
|
* or set to a default based on type.
|
2004-03-23 22:28:05 +01:00
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* @param dev Pointer to the device whose pci_ops you want to set.
|
2004-03-23 22:28:05 +01:00
|
|
|
* @see pci_drivers
|
|
|
|
*/
|
2003-04-22 21:02:15 +02:00
|
|
|
static void set_pci_ops(struct device *dev)
|
|
|
|
{
|
|
|
|
struct pci_driver *driver;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
if (dev->ops)
|
2003-04-22 21:02:15 +02:00
|
|
|
return;
|
2004-03-23 22:28:05 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Look through the list of setup drivers and find one for
|
2009-07-02 20:56:24 +02:00
|
|
|
* this PCI device.
|
2004-10-14 22:54:17 +02:00
|
|
|
*/
|
2009-07-02 20:56:24 +02:00
|
|
|
for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
|
2003-04-22 21:02:15 +02:00
|
|
|
if ((driver->vendor == dev->vendor) &&
|
2012-04-24 21:53:19 +02:00
|
|
|
device_id_match(driver, dev->device)) {
|
2009-10-27 22:49:33 +01:00
|
|
|
dev->ops = (struct device_operations *)driver->ops;
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
|
2010-11-05 00:23:47 +01:00
|
|
|
dev_path(dev), driver->vendor, driver->device,
|
|
|
|
(driver->ops->scan_bus ? "bus " : ""));
|
2003-04-24 08:25:08 +02:00
|
|
|
return;
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
}
|
2004-03-23 22:28:05 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* If I don't have a specific driver use the default operations. */
|
|
|
|
switch (dev->hdr_type & 0x7f) { /* Header type */
|
|
|
|
case PCI_HEADER_TYPE_NORMAL:
|
2003-04-22 21:02:15 +02:00
|
|
|
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
|
|
|
|
goto bad;
|
|
|
|
dev->ops = &default_pci_ops_dev;
|
|
|
|
break;
|
|
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
|
|
|
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
|
|
|
|
goto bad;
|
2005-07-08 04:49:49 +02:00
|
|
|
dev->ops = get_pci_bridge_ops(dev);
|
2003-04-22 21:02:15 +02:00
|
|
|
break;
|
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-05 15:29:32 +02:00
|
|
|
#if CONFIG_CARDBUS_PLUGIN_SUPPORT
|
2005-07-08 04:49:49 +02:00
|
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
|
|
|
dev->ops = &default_cardbus_ops_bus;
|
|
|
|
break;
|
|
|
|
#endif
|
2010-11-05 00:23:47 +01:00
|
|
|
default:
|
|
|
|
bad:
|
2004-04-29 22:08:54 +02:00
|
|
|
if (dev->enabled) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
|
|
|
|
"header type %02x, ignoring.\n", dev_path(dev),
|
|
|
|
dev->vendor, dev->device,
|
|
|
|
dev->class >> 8, dev->hdr_type);
|
2003-10-11 08:20:25 +02:00
|
|
|
}
|
2003-04-22 21:02:15 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* See if we have already allocated a device structure for a given devfn.
|
2004-03-23 22:28:05 +01:00
|
|
|
*
|
|
|
|
* Given a linked list of PCI device structures and a devfn number, find the
|
2004-12-03 23:39:34 +01:00
|
|
|
* device structure correspond to the devfn, if present. This function also
|
|
|
|
* removes the device structure from the linked list.
|
2004-03-23 22:28:05 +01:00
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* @param list The device structure list.
|
|
|
|
* @param devfn A device/function number.
|
|
|
|
* @return Pointer to the device structure found or NULL if we have not
|
2004-12-03 23:39:34 +01:00
|
|
|
* allocated a device for this devfn yet.
|
2003-04-22 21:02:15 +02:00
|
|
|
*/
|
2004-10-14 22:54:17 +02:00
|
|
|
static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
2004-10-14 22:54:17 +02:00
|
|
|
struct device *dev;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2004-10-14 22:54:17 +02:00
|
|
|
dev = 0;
|
2009-07-02 20:56:24 +02:00
|
|
|
for (; *list; list = &(*list)->sibling) {
|
2003-10-14 04:36:51 +02:00
|
|
|
if ((*list)->path.type != DEVICE_PATH_PCI) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_ERR, "child %s not a PCI device\n",
|
|
|
|
dev_path(*list));
|
2003-10-14 04:36:51 +02:00
|
|
|
continue;
|
|
|
|
}
|
2009-02-28 21:10:20 +01:00
|
|
|
if ((*list)->path.pci.devfn == devfn) {
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Unlink from the list. */
|
2003-04-22 21:02:15 +02:00
|
|
|
dev = *list;
|
|
|
|
*list = (*list)->sibling;
|
2009-07-02 20:56:24 +02:00
|
|
|
dev->sibling = NULL;
|
2003-04-22 21:02:15 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2009-07-02 20:56:24 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Just like alloc_dev() add the device to the list of devices on the
|
2009-07-02 20:56:24 +02:00
|
|
|
* bus. When the list of devices was formed we removed all of the
|
|
|
|
* parents children, and now we are interleaving static and dynamic
|
|
|
|
* devices in order on the bus.
|
2004-10-14 22:54:17 +02:00
|
|
|
*/
|
2003-09-02 05:36:25 +02:00
|
|
|
if (dev) {
|
2009-07-02 20:56:24 +02:00
|
|
|
struct device *child;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Find the last child of our parent. */
|
2010-11-05 00:23:47 +01:00
|
|
|
for (child = dev->bus->children; child && child->sibling;)
|
2003-09-02 05:36:25 +02:00
|
|
|
child = child->sibling;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Place the device on the list of children of its parent. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (child)
|
2003-09-02 05:36:25 +02:00
|
|
|
child->sibling = dev;
|
2010-11-05 00:23:47 +01:00
|
|
|
else
|
2003-09-02 05:36:25 +02:00
|
|
|
dev->bus->children = dev;
|
|
|
|
}
|
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
2009-05-12 00:24:53 +02:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Scan a PCI bus.
|
2005-07-08 04:49:49 +02:00
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* Determine the existence of a given PCI device. Allocate a new struct device
|
|
|
|
* if dev==NULL was passed in and the device exists in hardware.
|
2005-07-08 04:49:49 +02:00
|
|
|
*
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param dev Pointer to the dev structure.
|
|
|
|
* @param bus Pointer to the bus structure.
|
|
|
|
* @param devfn A device/function number to look at.
|
|
|
|
* @return The device structure for the device (if found), NULL otherwise.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
2010-10-17 21:01:48 +02:00
|
|
|
device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
|
2005-07-08 04:49:49 +02:00
|
|
|
{
|
2009-07-02 20:56:24 +02:00
|
|
|
u32 id, class;
|
|
|
|
u8 hdr_type;
|
2005-07-08 04:49:49 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Detect if a device is present. */
|
2005-07-08 04:49:49 +02:00
|
|
|
if (!dev) {
|
|
|
|
struct device dummy;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
dummy.bus = bus;
|
|
|
|
dummy.path.type = DEVICE_PATH_PCI;
|
2009-02-28 21:10:20 +01:00
|
|
|
dummy.path.pci.devfn = devfn;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Have we found something? Some broken boards return 0 if a
|
|
|
|
* slot is empty, but the expected answer is 0xffffffff.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
2010-11-05 00:23:47 +01:00
|
|
|
if (id == 0xffffffff)
|
2010-04-02 18:30:25 +02:00
|
|
|
return NULL;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2010-04-02 18:30:25 +02:00
|
|
|
if ((id == 0x00000000) || (id == 0x0000ffff) ||
|
|
|
|
(id == 0xffff0000)) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_SPEW, "%s, bad id 0x%x\n",
|
|
|
|
dev_path(&dummy), id);
|
2005-07-08 04:49:49 +02:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
dev = alloc_dev(bus, &dummy.path);
|
2009-07-02 20:56:24 +02:00
|
|
|
} else {
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Enable/disable the device. Once we have found the device-
|
2009-07-02 20:56:24 +02:00
|
|
|
* specific operations this operations we will disable the
|
|
|
|
* device with those as well.
|
2009-05-12 00:24:53 +02:00
|
|
|
*
|
2005-07-08 04:49:49 +02:00
|
|
|
* This is geared toward devices that have subfunctions
|
|
|
|
* that do not show up by default.
|
2009-05-12 00:24:53 +02:00
|
|
|
*
|
2005-07-08 04:49:49 +02:00
|
|
|
* If a device is a stuff option on the motherboard
|
2009-07-02 20:56:24 +02:00
|
|
|
* it may be absent and enable_dev() must cope.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Run the magic enable sequence for the device. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (dev->chip_ops && dev->chip_ops->enable_dev)
|
2005-07-08 04:49:49 +02:00
|
|
|
dev->chip_ops->enable_dev(dev);
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Now read the vendor and device ID. */
|
2005-07-08 04:49:49 +02:00
|
|
|
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* If the device does not have a PCI ID disable it. Possibly
|
2009-07-02 20:56:24 +02:00
|
|
|
* this is because we have already disabled the device. But
|
|
|
|
* this also handles optional devices that may not always
|
|
|
|
* show up.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
|
|
|
/* If the chain is fully enumerated quit */
|
2009-07-02 20:56:24 +02:00
|
|
|
if ((id == 0xffffffff) || (id == 0x00000000) ||
|
|
|
|
(id == 0x0000ffff) || (id == 0xffff0000)) {
|
2005-07-08 04:49:49 +02:00
|
|
|
if (dev->enabled) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_INFO, "PCI: Static device %s not "
|
|
|
|
"found, disabling it.\n", dev_path(dev));
|
2005-07-08 04:49:49 +02:00
|
|
|
dev->enabled = 0;
|
|
|
|
}
|
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Read the rest of the PCI configuration information. */
|
2005-07-08 04:49:49 +02:00
|
|
|
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
|
|
|
|
class = pci_read_config32(dev, PCI_CLASS_REVISION);
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Store the interesting information in the device structure. */
|
2005-07-08 04:49:49 +02:00
|
|
|
dev->vendor = id & 0xffff;
|
|
|
|
dev->device = (id >> 16) & 0xffff;
|
|
|
|
dev->hdr_type = hdr_type;
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
|
|
|
|
dev->class = class >> 8;
|
2005-07-08 04:49:49 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Architectural/System devices always need to be bus masters. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
|
2005-07-08 04:49:49 +02:00
|
|
|
dev->command |= PCI_COMMAND_MASTER;
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Look at the vendor and device ID, or at least the header type and
|
2009-07-02 20:56:24 +02:00
|
|
|
* class and figure out which set of configuration methods to use.
|
|
|
|
* Unless we already have some PCI ops.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
|
|
|
set_pci_ops(dev);
|
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Now run the magic enable/disable sequence for the device. */
|
2010-11-05 00:23:47 +01:00
|
|
|
if (dev->ops && dev->ops->enable)
|
2005-07-08 04:49:49 +02:00
|
|
|
dev->ops->enable(dev);
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* Display the device. */
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
|
|
|
|
dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
|
|
|
|
dev->ops ? "" : " No operations");
|
2005-07-08 04:49:49 +02:00
|
|
|
|
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
2013-06-15 16:16:56 +02:00
|
|
|
/**
|
|
|
|
* Test for match between romstage and ramstage device instance.
|
|
|
|
*
|
|
|
|
* @param dev Pointer to the device structure.
|
|
|
|
* @param sdev Simple device model identifier, created with PCI_DEV().
|
|
|
|
* @return Non-zero if bus:dev.fn of device matches.
|
|
|
|
*/
|
|
|
|
unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev)
|
|
|
|
{
|
|
|
|
return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) &&
|
|
|
|
dev->path.pci.devfn == PCI_DEV2DEVFN(sdev);
|
|
|
|
}
|
|
|
|
|
2009-05-12 00:24:53 +02:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Scan a PCI bus.
|
2004-03-23 22:28:05 +01:00
|
|
|
*
|
|
|
|
* Determine the existence of devices and bridges on a PCI bus. If there are
|
|
|
|
* bridges on the bus, recursively scan the buses behind the bridges.
|
|
|
|
*
|
2005-07-08 04:49:49 +02:00
|
|
|
* This function is the default scan_bus() method for the root device
|
|
|
|
* 'dev_root'.
|
|
|
|
*
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param bus Pointer to the bus structure.
|
|
|
|
* @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
|
|
|
|
* @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
|
|
|
|
* @param max Current bus number.
|
|
|
|
* @return The maximum bus number found, after scanning all subordinate busses.
|
2003-04-22 21:02:15 +02:00
|
|
|
*/
|
2010-11-05 00:23:47 +01:00
|
|
|
unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
|
|
|
|
unsigned max_devfn, unsigned int max)
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
|
|
|
unsigned int devfn;
|
2009-07-02 20:56:24 +02:00
|
|
|
struct device *old_devices;
|
|
|
|
struct device *child;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* Maximum sane devfn is 0xFF. */
|
2010-09-13 16:43:02 +02:00
|
|
|
if (max_devfn > 0xff) {
|
2010-11-05 00:23:47 +01:00
|
|
|
printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
|
|
|
|
"devfn %x\n", min_devfn, max_devfn);
|
|
|
|
printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
|
|
|
|
"Using 0xff.\n");
|
2010-09-13 16:43:02 +02:00
|
|
|
max_devfn=0xff;
|
|
|
|
}
|
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
old_devices = bus->children;
|
2009-07-02 20:56:24 +02:00
|
|
|
bus->children = NULL;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
|
|
|
post_code(0x24);
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Probe all devices/functions on this bus with some optimization for
|
2009-07-02 20:56:24 +02:00
|
|
|
* non-existence and single function devices.
|
2004-10-14 22:54:17 +02:00
|
|
|
*/
|
2003-09-02 05:36:25 +02:00
|
|
|
for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
|
2009-07-02 20:56:24 +02:00
|
|
|
struct device *dev;
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* First thing setup the device structure. */
|
2003-04-22 21:02:15 +02:00
|
|
|
dev = pci_scan_get_dev(&old_devices, devfn);
|
2004-10-14 23:25:53 +02:00
|
|
|
|
2009-07-02 20:56:24 +02:00
|
|
|
/* See if a device is present and setup the device structure. */
|
2009-05-12 00:24:53 +02:00
|
|
|
dev = pci_probe_dev(dev, bus, devfn);
|
2003-10-11 08:20:25 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* If this is not a multi function device, or the device is
|
2009-07-02 20:56:24 +02:00
|
|
|
* not present don't waste time probing another function.
|
2009-05-12 00:24:53 +02:00
|
|
|
* Skip to next device.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
2010-11-05 00:23:47 +01:00
|
|
|
if ((PCI_FUNC(devfn) == 0x00) && (!dev
|
2009-07-02 20:56:24 +02:00
|
|
|
|| (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
|
2003-04-22 21:02:15 +02:00
|
|
|
devfn += 0x07;
|
|
|
|
}
|
|
|
|
}
|
2010-11-05 00:23:47 +01:00
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
post_code(0x25);
|
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Warn if any leftover static devices are are found.
|
|
|
|
* There's probably a problem in devicetree.cb.
|
2009-07-02 20:56:24 +02:00
|
|
|
*/
|
|
|
|
if (old_devices) {
|
2005-07-08 04:49:49 +02:00
|
|
|
device_t left;
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_WARNING, "PCI: Left over static devices:\n");
|
2010-11-05 00:23:47 +01:00
|
|
|
for (left = old_devices; left; left = left->sibling)
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_WARNING, "%s\n", dev_path(left));
|
2010-11-05 00:23:47 +01:00
|
|
|
|
|
|
|
printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
|
2005-07-08 04:49:49 +02:00
|
|
|
}
|
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* For all children that implement scan_bus() (i.e. bridges)
|
2004-10-14 22:54:17 +02:00
|
|
|
* scan the bus behind that child.
|
|
|
|
*/
|
2010-11-05 00:23:47 +01:00
|
|
|
for (child = bus->children; child; child = child->sibling)
|
2005-07-08 04:49:49 +02:00
|
|
|
max = scan_bus(child, max);
|
2004-03-23 22:28:05 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* We've scanned the bus and so we know all about what's on the other
|
2009-07-02 20:56:24 +02:00
|
|
|
* side of any bridges that may be on this bus plus any devices.
|
2003-04-22 21:02:15 +02:00
|
|
|
* Return how far we've got finding sub-buses.
|
|
|
|
*/
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
|
2003-04-22 21:02:15 +02:00
|
|
|
post_code(0x55);
|
|
|
|
return max;
|
|
|
|
}
|
|
|
|
|
2004-03-23 22:28:05 +01:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Scan a PCI bridge and the buses behind the bridge.
|
2004-03-23 22:28:05 +01:00
|
|
|
*
|
|
|
|
* Determine the existence of buses behind the bridge. Set up the bridge
|
|
|
|
* according to the result of the scan.
|
|
|
|
*
|
|
|
|
* This function is the default scan_bus() method for PCI bridge devices.
|
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* @param dev Pointer to the bridge device.
|
|
|
|
* @param max The highest bus number assigned up to now.
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param do_scan_bus TODO
|
2009-07-02 20:56:24 +02:00
|
|
|
* @return The maximum bus number found, after scanning all subordinate buses.
|
2003-04-22 21:02:15 +02:00
|
|
|
*/
|
2009-05-12 00:24:53 +02:00
|
|
|
unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
|
2009-07-02 20:56:24 +02:00
|
|
|
unsigned int (*do_scan_bus) (struct bus * bus,
|
|
|
|
unsigned min_devfn,
|
|
|
|
unsigned max_devfn,
|
|
|
|
unsigned int max))
|
2003-04-22 21:02:15 +02:00
|
|
|
{
|
2003-09-02 05:36:25 +02:00
|
|
|
struct bus *bus;
|
2009-07-02 20:56:24 +02:00
|
|
|
u32 buses;
|
|
|
|
u16 cr;
|
2003-10-11 08:20:25 +02:00
|
|
|
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
|
2004-12-03 23:39:34 +01:00
|
|
|
|
2010-06-10 00:41:35 +02:00
|
|
|
if (dev->link_list == NULL) {
|
|
|
|
struct bus *link;
|
|
|
|
link = malloc(sizeof(*link));
|
|
|
|
if (link == NULL)
|
|
|
|
die("Couldn't allocate a link!\n");
|
|
|
|
memset(link, 0, sizeof(*link));
|
|
|
|
link->dev = dev;
|
|
|
|
dev->link_list = link;
|
|
|
|
}
|
|
|
|
|
|
|
|
bus = dev->link_list;
|
2003-09-02 05:36:25 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Set up the primary, secondary and subordinate bus numbers. We have
|
2003-04-22 21:02:15 +02:00
|
|
|
* no idea how many buses are behind this bridge yet, so we set the
|
2009-05-12 00:24:53 +02:00
|
|
|
* subordinate bus number to 0xff for the moment.
|
2004-10-14 22:54:17 +02:00
|
|
|
*/
|
2003-04-22 21:02:15 +02:00
|
|
|
bus->secondary = ++max;
|
|
|
|
bus->subordinate = 0xff;
|
2004-03-23 22:28:05 +01:00
|
|
|
|
2003-04-22 21:02:15 +02:00
|
|
|
/* Clear all status bits and turn off memory, I/O and master enables. */
|
2003-09-02 05:36:25 +02:00
|
|
|
cr = pci_read_config16(dev, PCI_COMMAND);
|
|
|
|
pci_write_config16(dev, PCI_COMMAND, 0x0000);
|
|
|
|
pci_write_config16(dev, PCI_STATUS, 0xffff);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Read the existing primary/secondary/subordinate bus
|
2004-10-14 22:54:17 +02:00
|
|
|
* number configuration.
|
|
|
|
*/
|
2003-09-02 05:36:25 +02:00
|
|
|
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
|
2003-04-22 21:02:15 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* Configure the bus numbers for this bridge: the configuration
|
2003-04-22 21:02:15 +02:00
|
|
|
* transactions will not be propagated by the bridge if it is not
|
2004-10-14 22:54:17 +02:00
|
|
|
* correctly configured.
|
|
|
|
*/
|
2003-04-22 21:02:15 +02:00
|
|
|
buses &= 0xff000000;
|
2009-07-02 20:56:24 +02:00
|
|
|
buses |= (((unsigned int)(dev->bus->secondary) << 0) |
|
|
|
|
((unsigned int)(bus->secondary) << 8) |
|
|
|
|
((unsigned int)(bus->subordinate) << 16));
|
2003-09-02 05:36:25 +02:00
|
|
|
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
|
2004-12-03 23:39:34 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* Now we can scan all subordinate buses (those behind the bridge). */
|
2005-07-08 04:49:49 +02:00
|
|
|
max = do_scan_bus(bus, 0x00, 0xff, max);
|
2004-12-03 23:39:34 +01:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/*
|
|
|
|
* We know the number of buses behind this bridge. Set the subordinate
|
2004-10-14 22:54:17 +02:00
|
|
|
* bus number to its real value.
|
|
|
|
*/
|
2003-04-22 21:02:15 +02:00
|
|
|
bus->subordinate = max;
|
2009-07-02 20:56:24 +02:00
|
|
|
buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
|
2003-09-02 05:36:25 +02:00
|
|
|
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
|
|
|
|
pci_write_config16(dev, PCI_COMMAND, cr);
|
2009-05-12 00:24:53 +02:00
|
|
|
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
|
2003-04-22 21:02:15 +02:00
|
|
|
return max;
|
|
|
|
}
|
2004-03-23 22:28:05 +01:00
|
|
|
|
2005-07-08 04:49:49 +02:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Scan a PCI bridge and the buses behind the bridge.
|
2005-07-08 04:49:49 +02:00
|
|
|
*
|
|
|
|
* Determine the existence of buses behind the bridge. Set up the bridge
|
|
|
|
* according to the result of the scan.
|
|
|
|
*
|
|
|
|
* This function is the default scan_bus() method for PCI bridge devices.
|
|
|
|
*
|
2009-07-02 20:56:24 +02:00
|
|
|
* @param dev Pointer to the bridge device.
|
|
|
|
* @param max The highest bus number assigned up to now.
|
|
|
|
* @return The maximum bus number found, after scanning all subordinate buses.
|
|
|
|
*/
|
|
|
|
unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
|
|
|
|
{
|
|
|
|
return do_pci_scan_bridge(dev, max, pci_scan_bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Scan a PCI domain.
|
2009-07-02 20:56:24 +02:00
|
|
|
*
|
|
|
|
* This function is the default scan_bus() method for PCI domains.
|
|
|
|
*
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param dev Pointer to the domain.
|
|
|
|
* @param max The highest bus number assigned up to now.
|
|
|
|
* @return The maximum bus number found, after scanning all subordinate busses.
|
2005-07-08 04:49:49 +02:00
|
|
|
*/
|
2009-07-02 20:56:24 +02:00
|
|
|
unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
|
2005-07-08 04:49:49 +02:00
|
|
|
{
|
2010-06-10 00:41:35 +02:00
|
|
|
max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
|
2009-07-02 20:56:24 +02:00
|
|
|
return max;
|
2005-07-08 04:49:49 +02:00
|
|
|
}
|
|
|
|
|
PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-05-13 05:46:31 +02:00
|
|
|
/**
|
|
|
|
* Take an INT_PIN number (0, 1 - 4) and convert
|
|
|
|
* it to a string ("NO PIN", "PIN A" - "PIN D")
|
|
|
|
*
|
|
|
|
* @param pin PCI Interrupt Pin number (0, 1 - 4)
|
|
|
|
* @return A string corresponding to the pin number or "Invalid"
|
|
|
|
*/
|
|
|
|
const char *pin_to_str(int pin)
|
|
|
|
{
|
|
|
|
const char *str[5] = {
|
|
|
|
"NO PIN",
|
|
|
|
"PIN A",
|
|
|
|
"PIN B",
|
|
|
|
"PIN C",
|
|
|
|
"PIN D",
|
|
|
|
};
|
|
|
|
|
|
|
|
if (pin >= 0 && pin <= 4)
|
|
|
|
return str[pin];
|
|
|
|
else
|
|
|
|
return "Invalid PIN, not 0 - 4";
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Get the PCI INT_PIN swizzle for a device defined as:
|
|
|
|
* pin_parent = (pin_child + devn_child) % 4 + 1
|
|
|
|
* where PIN A = 1 ... PIN_D = 4
|
|
|
|
*
|
|
|
|
* Given a PCI device structure 'dev', find the interrupt pin
|
|
|
|
* that will be triggered on its parent bridge device when
|
|
|
|
* generating an interrupt. For example: Device 1:3.2 may
|
|
|
|
* use INT_PIN A but will trigger PIN D on its parent bridge
|
|
|
|
* device. In this case, this function will return 4 (PIN D).
|
|
|
|
*
|
|
|
|
* @param dev A PCI device structure to swizzle interrupt pins for
|
2015-01-05 00:54:35 +01:00
|
|
|
* @param *parent_bridge The PCI device structure for the bridge
|
PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-05-13 05:46:31 +02:00
|
|
|
* device 'dev' is attached to
|
|
|
|
* @return The interrupt pin number (1 - 4) that 'dev' will
|
|
|
|
* trigger when generating an interrupt
|
|
|
|
*/
|
|
|
|
static int swizzle_irq_pins(device_t dev, device_t *parent_bridge)
|
|
|
|
{
|
|
|
|
device_t parent; /* Our current device's parent device */
|
|
|
|
device_t child; /* The child device of the parent */
|
|
|
|
uint8_t parent_bus = 0; /* Parent Bus number */
|
|
|
|
uint16_t parent_devfn = 0; /* Parent Device and Function number */
|
|
|
|
uint16_t child_devfn = 0; /* Child Device and Function number */
|
|
|
|
uint8_t swizzled_pin = 0; /* Pin swizzled across a bridge */
|
|
|
|
|
|
|
|
/* Start with PIN A = 0 ... D = 3 */
|
|
|
|
swizzled_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN) - 1;
|
|
|
|
|
|
|
|
/* While our current device has parent devices */
|
|
|
|
child = dev;
|
|
|
|
for (parent = child->bus->dev; parent; parent = parent->bus->dev) {
|
|
|
|
parent_bus = parent->bus->secondary;
|
|
|
|
parent_devfn = parent->path.pci.devfn;
|
|
|
|
child_devfn = child->path.pci.devfn;
|
|
|
|
|
|
|
|
/* Swizzle the INT_PIN for any bridges not on root bus */
|
|
|
|
swizzled_pin = (PCI_SLOT(child_devfn) + swizzled_pin) % 4;
|
|
|
|
printk(BIOS_SPEW, "\tWith INT_PIN swizzled to %s\n"
|
|
|
|
"\tAttached to bridge device %01X:%02Xh.%02Xh\n",
|
|
|
|
pin_to_str(swizzled_pin + 1), parent_bus,
|
|
|
|
PCI_SLOT(parent_devfn), PCI_FUNC(parent_devfn));
|
|
|
|
|
|
|
|
/* Continue until we find the root bus */
|
|
|
|
if (parent_bus > 0) {
|
|
|
|
/*
|
|
|
|
* We will go on to the next parent so this parent
|
|
|
|
* becomes the child
|
|
|
|
*/
|
|
|
|
child = parent;
|
|
|
|
continue;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Found the root bridge device,
|
|
|
|
* fill in the structure and exit
|
|
|
|
*/
|
|
|
|
*parent_bridge = parent;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* End with PIN A = 1 ... D = 4 */
|
|
|
|
return swizzled_pin + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Given a device structure 'dev', find its interrupt pin
|
|
|
|
* and its parent bridge 'parent_bdg' device structure.
|
|
|
|
* If it is behind a bridge, it will return the interrupt
|
|
|
|
* pin number (1 - 4) of the parent bridge that the device
|
|
|
|
* interrupt pin has been swizzled to, otherwise it will
|
|
|
|
* return the interrupt pin that is programmed into the
|
|
|
|
* PCI config space of the target device. If 'dev' is
|
|
|
|
* behind a bridge, it will fill in 'parent_bdg' with the
|
|
|
|
* device structure of the bridge it is behind, otherwise
|
|
|
|
* it will copy 'dev' into 'parent_bdg'.
|
|
|
|
*
|
|
|
|
* @param dev A PCI device structure to get interrupt pins for.
|
|
|
|
* @param *parent_bdg The PCI device structure for the bridge
|
|
|
|
* device 'dev' is attached to.
|
|
|
|
* @return The interrupt pin number (1 - 4) that 'dev' will
|
|
|
|
* trigger when generating an interrupt.
|
|
|
|
* Errors: -1 is returned if the device is not enabled
|
|
|
|
* -2 is returned if a parent bridge could not be found.
|
|
|
|
*/
|
|
|
|
int get_pci_irq_pins(device_t dev, device_t *parent_bdg)
|
|
|
|
{
|
|
|
|
uint8_t bus = 0; /* The bus this device is on */
|
|
|
|
uint16_t devfn = 0; /* This device's device and function numbers */
|
|
|
|
uint8_t int_pin = 0; /* Interrupt pin used by the device */
|
|
|
|
uint8_t target_pin = 0; /* Interrupt pin we want to assign an IRQ to */
|
|
|
|
|
|
|
|
/* Make sure this device is enabled */
|
|
|
|
if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI)))
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
bus = dev->bus->secondary;
|
|
|
|
devfn = dev->path.pci.devfn;
|
|
|
|
|
|
|
|
/* Get and validate the interrupt pin used. Only 1-4 are allowed */
|
|
|
|
int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
|
|
|
|
if (int_pin < 1 || int_pin > 4)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
printk(BIOS_SPEW, "PCI IRQ: Found device %01X:%02X.%02X using %s\n",
|
|
|
|
bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pin_to_str(int_pin));
|
|
|
|
|
|
|
|
/* If this device is on a bridge, swizzle its INT_PIN */
|
|
|
|
if (bus) {
|
|
|
|
/* Swizzle its INT_PINs */
|
|
|
|
target_pin = swizzle_irq_pins(dev, parent_bdg);
|
|
|
|
|
|
|
|
/* Make sure the swizzle returned valid structures */
|
|
|
|
if (parent_bdg == NULL) {
|
|
|
|
printk(BIOS_WARNING,
|
|
|
|
"Warning: Could not find parent bridge for this device!\n");
|
|
|
|
return -2;
|
|
|
|
}
|
|
|
|
} else { /* Device is not behind a bridge */
|
|
|
|
target_pin = int_pin; /* Return its own interrupt pin */
|
|
|
|
*parent_bdg = dev; /* Return its own structure */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Target pin is the interrupt pin we want to assign an IRQ to */
|
|
|
|
return target_pin;
|
|
|
|
}
|
|
|
|
|
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-05 15:29:32 +02:00
|
|
|
#if CONFIG_PC80_SYSTEM
|
2009-07-02 20:56:24 +02:00
|
|
|
/**
|
2010-10-17 21:01:48 +02:00
|
|
|
* Assign IRQ numbers.
|
2009-07-02 20:56:24 +02:00
|
|
|
*
|
2009-07-21 23:36:41 +02:00
|
|
|
* This function assigns IRQs for all functions contained within the indicated
|
2010-11-05 00:23:47 +01:00
|
|
|
* device address. If the device does not exist or does not require interrupts
|
2009-07-21 23:36:41 +02:00
|
|
|
* then this function has no effect.
|
2009-07-02 20:56:24 +02:00
|
|
|
*
|
|
|
|
* This function should be called for each PCI slot in your system.
|
|
|
|
*
|
2010-10-17 21:01:48 +02:00
|
|
|
* @param bus Pointer to the bus structure.
|
|
|
|
* @param slot TODO
|
|
|
|
* @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD
|
|
|
|
* of this slot. The particular IRQ #s that are passed in depend on the
|
|
|
|
* routing inside your southbridge and on your board.
|
2009-07-21 23:36:41 +02:00
|
|
|
*/
|
2005-07-08 04:49:49 +02:00
|
|
|
void pci_assign_irqs(unsigned bus, unsigned slot,
|
2010-11-05 00:23:47 +01:00
|
|
|
const unsigned char pIntAtoD[4])
|
2003-10-02 02:08:42 +02:00
|
|
|
{
|
2009-07-21 23:36:41 +02:00
|
|
|
unsigned int funct;
|
|
|
|
device_t pdev;
|
2010-11-05 00:23:47 +01:00
|
|
|
u8 line, irq;
|
2009-07-21 23:36:41 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* Each slot may contain up to eight functions. */
|
2009-07-21 23:36:41 +02:00
|
|
|
for (funct = 0; funct < 8; funct++) {
|
|
|
|
pdev = dev_find_slot(bus, (slot << 3) + funct);
|
|
|
|
|
|
|
|
if (!pdev)
|
|
|
|
continue;
|
2003-10-02 02:08:42 +02:00
|
|
|
|
2009-07-21 23:36:41 +02:00
|
|
|
line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
|
2003-10-02 02:08:42 +02:00
|
|
|
|
2010-11-05 00:23:47 +01:00
|
|
|
/* PCI spec says all values except 1..4 are reserved. */
|
2009-07-21 23:36:41 +02:00
|
|
|
if ((line < 1) || (line > 4))
|
|
|
|
continue;
|
2003-10-02 02:08:42 +02:00
|
|
|
|
2009-07-21 23:36:41 +02:00
|
|
|
irq = pIntAtoD[line - 1];
|
2003-10-02 02:08:42 +02:00
|
|
|
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
|
2010-11-05 00:23:47 +01:00
|
|
|
irq, bus, slot, funct);
|
2003-10-02 02:08:42 +02:00
|
|
|
|
2010-04-27 08:56:47 +02:00
|
|
|
pci_write_config8(pdev, PCI_INTERRUPT_LINE,
|
2010-11-05 00:23:47 +01:00
|
|
|
pIntAtoD[line - 1]);
|
2003-10-02 02:08:42 +02:00
|
|
|
|
2009-07-21 23:36:41 +02:00
|
|
|
#ifdef PARANOID_IRQ_ASSIGNMENTS
|
2009-10-07 20:41:08 +02:00
|
|
|
irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, " Readback = %d\n", irq);
|
2009-07-21 23:36:41 +02:00
|
|
|
#endif
|
2003-10-02 02:08:42 +02:00
|
|
|
|
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-05 15:29:32 +02:00
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#if CONFIG_PC80_SYSTEM
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2010-11-05 00:23:47 +01:00
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/* Change to level triggered. */
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i8259_configure_irq_trigger(pIntAtoD[line - 1],
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IRQ_LEVEL_TRIGGERED);
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2010-12-17 00:52:04 +01:00
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#endif
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2003-10-02 02:08:42 +02:00
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}
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}
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2009-07-21 23:36:41 +02:00
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#endif
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