GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/soc/intel/apollolake/Makefile.inc

67 lines
1.7 KiB
PHP
Raw Normal View History

soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
soc/apollolake: Enable all CPU cores using the parallel MP lib This is the minimal setup needed to get all CPU cores enabled. That includes sending an IPI to APs and setting up MTRRs. Microcode updates are not performed for two reasons: * CSE (Converged Security Engine) upgrades the microcode before releasing reset * Microcode update files are not available at this point in time Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-05 06:33:04 +01:00
subdirs-y += ../../../cpu/x86/cache
soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-07 02:16:41 +02:00
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 02:47:03 +01:00
bootblock-y += bootblock/bootblock.c
soc/intel/apollolake: use CAR code coherency for all CAR stages The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image is flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14210 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-31 18:38:13 +02:00
bootblock-y += car.c
soc/apollolake: Add minimal GPIO driver This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-10 02:02:57 +01:00
bootblock-y += gpio.c
soc/apollolake/lpc: Open I/O to LPC based on resource allocation Besides a number of fixed memory windows, Apollolake supports opening a configureable 64 KiB MMIO window, as well as four PMIO windows to the LPC bus. Open up these windows dynamically, based on how resources were allocated to the child LPC devices. Change-Id: I170e861693cb6fd1be38889adc951f197a13460f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-30 21:09:05 +02:00
bootblock-y += lpc_lib.c
soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-13 00:12:43 +01:00
bootblock-y += mmap_boot.c
soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-07 02:16:41 +02:00
bootblock-y += placeholders.c
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 02:47:03 +01:00
bootblock-y += tsc_freq.c
soc/intel/apollolake: group serial console options into one Kconfig Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/13790 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-25 01:49:07 +01:00
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-07 02:16:41 +02:00
soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
romstage-y += placeholders.c
soc/intel/apollolake: use CAR code coherency for all CAR stages The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image is flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14210 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-31 18:38:13 +02:00
romstage-y += car.c
soc/intel/apollolake: Add romstage that calls FSP2.0 driver This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-26 02:42:25 +01:00
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
soc/apollolake: Add minimal GPIO driver This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-10 02:02:57 +01:00
romstage-y += gpio.c
soc/intel/apollolake: group serial console options into one Kconfig Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/13790 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-25 01:49:07 +01:00
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
soc/apollolake/lpc: Open I/O to LPC based on resource allocation Besides a number of fixed memory windows, Apollolake supports opening a configureable 64 KiB MMIO window, as well as four PMIO windows to the LPC bus. Open up these windows dynamically, based on how resources were allocated to the child LPC devices. Change-Id: I170e861693cb6fd1be38889adc951f197a13460f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-30 21:09:05 +02:00
romstage-y += lpc_lib.c
soc/intel/apollolake: Add cbmem_top() implementation On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-03 00:09:27 +01:00
romstage-y += memmap.c
soc/intel/apollolake: provide common LPDDR4 memory init Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. Change-Id: I686eb3097c33399a3b94af89237f7fe1b2d34c2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14790 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12 19:43:37 +02:00
romstage-y += meminit.c
soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-13 00:12:43 +01:00
romstage-y += mmap_boot.c
soc/intel/apollolake: Add tsc_freq.c to all the stages Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14339 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13 02:00:52 +02:00
romstage-y += tsc_freq.c
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
romstage-y += pmutil.c
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 02:47:03 +01:00
soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
smm-y += placeholders.c
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
smm-y += pmutil.c
soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13348 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-10 02:06:34 +01:00
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
soc/apollolake: Enable all CPU cores using the parallel MP lib This is the minimal setup needed to get all CPU cores enabled. That includes sending an IPI to APs and setting up MTRRs. Microcode updates are not performed for two reasons: * CSE (Converged Security Engine) upgrades the microcode before releasing reset * Microcode update files are not available at this point in time Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-05 06:33:04 +01:00
ramstage-y += cpu.c
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
ramstage-y += chip.c
soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
ramstage-y += placeholders.c
soc/apollolake: Add minimal GPIO driver This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-10 02:02:57 +01:00
ramstage-y += gpio.c
soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
ramstage-y += graphics.c
soc/intel/apollolake: group serial console options into one Kconfig Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/13790 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-25 01:49:07 +01:00
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
soc/apollolake: Add lpc device driver A dedicated pci device driver required for LPC devices as the legacy IO range need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver system will have assertion on load RTC DXE driver in UEFI payloads. Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-13 03:19:41 +01:00
ramstage-y += lpc.c
soc/apollolake/lpc: Open I/O to LPC based on resource allocation Besides a number of fixed memory windows, Apollolake supports opening a configureable 64 KiB MMIO window, as well as four PMIO windows to the LPC bus. Open up these windows dynamically, based on how resources were allocated to the child LPC devices. Change-Id: I170e861693cb6fd1be38889adc951f197a13460f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-30 21:09:05 +02:00
ramstage-y += lpc_lib.c
soc/intel/apollolake: Add cbmem_top() implementation On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-03 00:09:27 +01:00
ramstage-y += memmap.c
soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-13 00:12:43 +01:00
ramstage-y += mmap_boot.c
soc/intel/apollolake: Avoid UART BAR relocation at ramstage UART bar gets overwritten during resource allocation stage. As result the serial driver ends up using stale BAR so serial output does not work. This driver simply tells resource allocator not to change BAR of UART device. Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-09 01:12:06 +01:00
ramstage-y += uart.c
soc/apollolake: Add memory and reserve MMIO resources This adds most important MMIO reserved memory resources, real DRAM memory resources, and some DRAM resources that can not be used as RAM for whatever reason. Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-16 03:05:12 +01:00
ramstage-y += northbridge.c
soc/intel/apollolake: Implement SPI controller driver Implement flash read, write, and erase functionality using the hardware sequencing capabilities of the SOC. Due to changes in hardware requirements, the flash chip must be probed differently than on previous platforms (details explained in comments). Note that this is a minimal implementation, and does not provide all the bells and whistles. Change-Id: I6dcc3bc36dfce61927d126d231a16d485acb1bdc Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-25 00:08:23 +01:00
ramstage-y += spi.c
soc/intel/apollolake: Add tsc_freq.c to all the stages Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14339 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13 02:00:52 +02:00
ramstage-y += tsc_freq.c
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
ramstage-y += pmutil.c
soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
ramstage-y += pmc.c
soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
soc/intel/apollolake: utilize postcar phase/stage The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-18 17:19:38 +01:00
postcar-y += exit_car.S
postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
soc/intel/apollolake: Enable CACHE_MRC_SETTINGS This enables CACHE_MRC_SETTINGS by default as well selects timer configuration. Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14252 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 01:38:51 +01:00
postcar-y += tsc_freq.c
soc/intel/apollolake: utilize postcar phase/stage The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-18 17:19:38 +01:00
soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-07 02:16:41 +02:00
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
soc/intel/apollolake: Relocate FSP-M during insertion in CBFS Since FSP-M is run in CAR (as opposed to XIP), its default link address may need to be changed. Since cbfstool can relocate FSP blobs, take advantage of that feature. Change-Id: I4353fe09d785c090843ce25ff4e654d45c64c381 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14866 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17 09:03:27 +02:00
# Since FSP-M runs in CAR we need to relocate it to a specific address
$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06 19:33:49 +02:00
endif
Reference in a new issue Copy permalink