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move single options out of main menu and remove stray "options" Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 03:27:53 +01:00
menu "Console"
WIP: Add support for non-8250 built-in UARTs Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 02:31:37 +01:00
ARM: Separate the early console (romstage) from the bootblock console. It might be that you want an early console in romstage before RAM is up, but you can't or don't want to support the console all the way back in the bootblock. By making the console in those two different environments configurable seperately that becomes possible. On the 5250 console output as early as the bootblock works, but on the 5420 it only starts working in the ROM stage after clocks have been initialized. Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3671 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 09:21:20 +02:00
config BOOTBLOCK_CONSOLE
bool "Enable early (bootblock) console output."
Simplify early / bootblock console code Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-19 22:42:00 +02:00
depends on ARCH_ARMV7
default n
ARM: Separate the early console (romstage) from the bootblock console. It might be that you want an early console in romstage before RAM is up, but you can't or don't want to support the console all the way back in the bootblock. By making the console in those two different environments configurable seperately that becomes possible. On the 5250 console output as early as the bootblock works, but on the 5420 it only starts working in the ROM stage after clocks have been initialized. Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3671 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 09:21:20 +02:00
help
Use console during the bootblock if supported
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
config EARLY_CONSOLE
bool "Enable early (pre-RAM) console output."
Make EARLY_CONSOLE optional This change brings back the possibility to disable console output while in romstage, like before commit d2f45c65. For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM CONSOLE do not work correctly for romstage due the way cache-as-ram is set up, but might already work for ramstage. Change-Id: Id8d830e02a18129af419d3b5860866acf315d531 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3846 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-31 19:52:04 +02:00
default y if CACHE_AS_RAM
Simplify early / bootblock console code Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-19 22:42:00 +02:00
default n
make early serial console support more generic This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. The UART code structure needs some rework, but the use of ROMCC, romstage, and then ramstage makes things complex. uart.h now includes all .h files for all uarts. All 2 of them. This is actually a simplifying change. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2086 Tested-by: build bot (Jenkins)
2013-01-01 02:28:43 +01:00
help
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
Use console during early (pre-RAM) boot stages
console: Squelch console output from AP CPUs in romstage Add Kconfig option SQUELCH_EARLY_SMP and have it enabled by default. Console drivers have unpredictable results if multiple threads attempt to share same resources without spinlock. Serial UARTs have not had huge problems, only distorted output, but those relying on cache-as-ram (CBMEM and usbdebug) may require this. Change-Id: I7f406fdea7b6dc6a341c4da2fab56f7b7ff568b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3854 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-12 22:29:57 +02:00
config SQUELCH_EARLY_SMP
bool "Squelch AP CPUs from early console."
default y
depends on EARLY_CONSOLE
help
When selected only the BSP CPU will output to early console.
Console drivers have unpredictable behaviour if multiple threads
attempt to share the same resources without a spinlock.
If unsure, say Y.
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
config CONSOLE_SERIAL
bool "Serial port console output"
default y
help
Send coreboot debug output to a serial port (should be one or more of
CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART)
make early serial console support more generic This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. The UART code structure needs some rework, but the use of ROMCC, romstage, and then ramstage makes things complex. uart.h now includes all .h files for all uarts. All 2 of them. This is actually a simplifying change. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2086 Tested-by: build bot (Jenkins)
2013-01-01 02:28:43 +01:00
WIP: Add support for non-8250 built-in UARTs Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 02:31:37 +01:00
config CONSOLE_SERIAL8250
bool "Serial port console output (I/O mapped, 8250-compatible)"
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
depends on CONSOLE_SERIAL
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27 01:47:04 +02:00
depends on HAVE_UART_IO_MAPPED
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
default y
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
help
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27 01:47:04 +02:00
Send coreboot debug output to an I/O mapped serial port console.
config CONSOLE_SERIAL8250MEM
WIP: Add support for non-8250 built-in UARTs Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 02:31:37 +01:00
bool "Serial port console output (memory mapped, 8250-compatible)"
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
depends on CONSOLE_SERIAL
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27 01:47:04 +02:00
depends on HAVE_UART_MEMORY_MAPPED
help
Send coreboot debug output to a memory mapped serial port console.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
config CONSOLE_SERIAL_UART
bool "Serial port console output (device-specific UART)"
depends on CONSOLE_SERIAL
depends on HAVE_UART_SPECIAL
default y
WIP: Add support for non-8250 built-in UARTs Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 02:31:37 +01:00
help
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
Send coreboot debug output to a device-specific serial port console.
WIP: Add support for non-8250 built-in UARTs Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 02:31:37 +01:00
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
choice
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
prompt "Serial port for 8250"
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
default CONSOLE_SERIAL_COM1
depends on CONSOLE_SERIAL8250
config CONSOLE_SERIAL_COM1
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
bool "COM1/ttyS0, I/O port 0x3f8"
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Serial console on COM1/ttyS0 at I/O port 0x3f8.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_COM2
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
bool "COM2/ttyS1, I/O port 0x2f8"
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Serial console on COM2/ttyS1 at I/O port 0x2f8.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_COM3
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
bool "COM3/ttyS2, I/O port 0x3e8"
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Serial console on COM3/ttyS2 at I/O port 0x3e8.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_COM4
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
bool "COM4/ttyS3, I/O port 0x2e8"
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Serial console on COM4/ttyS3 at I/O port 0x2e8.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
endchoice
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
config TTYS0_BASE
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
hex
Rename CONFIG_SERIAL_CONSOLE to match newconfig. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 19:24:08 +02:00
depends on CONSOLE_SERIAL8250
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
default 0x3f8 if CONSOLE_SERIAL_COM1
default 0x2f8 if CONSOLE_SERIAL_COM2
default 0x3e8 if CONSOLE_SERIAL_COM3
default 0x2e8 if CONSOLE_SERIAL_COM4
help
Map the COM port names to the respective I/O port.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
choice
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
prompt "Baud rate"
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
default CONSOLE_SERIAL_115200
console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 14:24:12 +01:00
depends on CONSOLE_SERIAL
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_115200
bool "115200"
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Set serial port Baud rate to 115200.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_57600
bool "57600"
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Set serial port Baud rate to 57600.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_38400
bool "38400"
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Set serial port Baud rate to 38400.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_19200
bool "19200"
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Set serial port Baud rate to 19200.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config CONSOLE_SERIAL_9600
bool "9600"
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Set serial port Baud rate to 9600.
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
endchoice
WIP: Add support for non-8250 built-in UARTs Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 02:31:37 +01:00
#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 00:39:55 +02:00
config TTYS0_BAUD
int
default 115200 if CONSOLE_SERIAL_115200
default 57600 if CONSOLE_SERIAL_57600
default 38400 if CONSOLE_SERIAL_38400
default 19200 if CONSOLE_SERIAL_19200
default 9600 if CONSOLE_SERIAL_9600
help
Various smaller console option fixes as suggested by Peter Stuge: - Change "COM port" to "Serial port". - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for easy recognition by the average user. - Change BAUD to Baud. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 00:52:34 +01:00
Map the Baud rates to an integer.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
# TODO: Allow user-friendly selection of settings other than 8n1.
Various fixes to Kconfig: All kconfig-boards should have a complete set of variables now, though they might still have the wrong values. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 22:48:07 +02:00
config TTYS0_LCS
int
default 3
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27 01:47:04 +02:00
depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
Various fixes to Kconfig: All kconfig-boards should have a complete set of variables now, though they might still have the wrong values. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 22:48:07 +02:00
spkmodem console Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2987 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-30 02:02:13 +01:00
config SPKMODEM
bool "spkmodem (console on speaker) console output"
default n
help
Send coreboot debug output through speaker
Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26 09:35:55 +02:00
# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
config HAVE_USBDEBUG
usbdebug: Support choice of EHCI controller Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-15 15:27:06 +02:00
bool
default y if HAVE_USBDEBUG_OPTIONS
default n
# Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple
# EHCI controllers or multiple ports with Debug Port capability
config HAVE_USBDEBUG_OPTIONS
Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26 09:35:55 +02:00
def_bool n
also rename the config option. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-25 19:09:05 +02:00
config USBDEBUG
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
bool "USB 2.0 EHCI debug dongle support"
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
default n
Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26 09:35:55 +02:00
depends on HAVE_USBDEBUG
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
help
This option allows you to use a so-called USB EHCI Debug device
Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26 09:35:55 +02:00
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Linux "EHCI Debug Device gadget" driver found in recent kernel)
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).
This feature is NOT supported on all chipsets in coreboot!
It also requires a USB2 controller which supports the EHCI
Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26 09:35:55 +02:00
Debug Port capability.
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.
If unsure, say N.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
usbdebug: Fix boards without EARLY_CBMEM_INIT The main usbdebug file lib/usbdebug.c was removed from romstage build with commit f8bf5a10 but the chipset-specific parts were not, leading to unresolved symbol errors for AMD platforms. Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient use of this feature. Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-11 20:14:59 +02:00
config USBDEBUG_IN_ROMSTAGE
bool
default y if USBDEBUG && EARLY_CBMEM_INIT && EARLY_CONSOLE
default n
usbdebug: Allow an USB hub on the debug dongle Some development kits with USB 2.0 HS OTG have an USB hub instead of being directly connected to the USB host/device controller. Send the necessary initialisation sequence, using HUB CLASS requests of PORT_POWER and PORT_RESET to enable a pre-selected port number where a device supporting debug descriptor is located. This also adds the Kconfig option for BeagleBone. Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3925 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-23 22:33:16 +02:00
if USBDEBUG
usbdebug: Support choice of EHCI controller Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-15 15:27:06 +02:00
config USBDEBUG_HCD_INDEX
int "Index for EHCI controller to use with usbdebug"
default 0
help
Some boards have multiple EHCI controllers with possibly only
one having the Debug Port capability on an external USB port.
Mapping of this index to PCI device functions is southbridge
specific and mainboard level Kconfig should already provide
a working default value here.
Add a kconfig option to allow the user to select a specific physical USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 20:03:18 +02:00
config USBDEBUG_DEFAULT_PORT
int "Default USB port to use as Debug Port"
usbdebug: Change debug port scanning On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-12 19:40:37 +02:00
default 0
Add a kconfig option to allow the user to select a specific physical USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 20:03:18 +02:00
help
usbdebug: Change debug port scanning On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-12 19:40:37 +02:00
Selects which physical USB port usbdebug dongle is connected to.
Setting of 0 means to scan possible ports starting from 1.
Add a kconfig option to allow the user to select a specific physical USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 20:03:18 +02:00
usbdebug: Change debug port scanning On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-12 19:40:37 +02:00
Intel platforms have hardwired the debug port location and this
setting makes no difference there.
Add a kconfig option to allow the user to select a specific physical USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 20:03:18 +02:00
Hence, if you select the correct port here, you can speed up
usbdebug: Change debug port scanning On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-12 19:40:37 +02:00
your boot time. Which USB port number refers to which actual
port on your mainboard (potentially also USB pin headers on
your mainboard) is highly board-specific, and you'll likely
Add a kconfig option to allow the user to select a specific physical USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 20:03:18 +02:00
have to find out by trial-and-error.
usbdebug: Allow an USB hub on the debug dongle Some development kits with USB 2.0 HS OTG have an USB hub instead of being directly connected to the USB host/device controller. Send the necessary initialisation sequence, using HUB CLASS requests of PORT_POWER and PORT_RESET to enable a pre-selected port number where a device supporting debug descriptor is located. This also adds the Kconfig option for BeagleBone. Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3925 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-23 22:33:16 +02:00
choice
prompt "Type of dongle"
default USBDEBUG_DONGLE_STD
config USBDEBUG_DONGLE_STD
bool "Net20DC or compatible"
config USBDEBUG_DONGLE_BEAGLEBONE
bool "BeagleBone"
help
Use this to configure the USB hub on BeagleBone board.
endchoice
config USBDEBUG_OPTIONAL_HUB_PORT
int
default 2 if USBDEBUG_DONGLE_BEAGLEBONE
default 0
endif # USBDEBUG
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
# TODO: Deps?
# TODO: Improve description.
Printing coreboot debug messages on VGA console is pretty much useless, since initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 09:09:50 +01:00
config ONBOARD_VGA_IS_PRIMARY
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
bool "Use onboard VGA as primary video device"
tables.diff: Add Kconfig dialogues for ACPI, MP_TABLE, ... Kconfig_bools.diff: Change some more ints to bools, change some default values. xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB. smp.diff: set CONFIG_SMP based on MAX_CPUS. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 20:49:08 +02:00
default n
help
If not selected, the last adapter found will be used.
Add support for the console over Ethernet (through PCI NE2000). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-16 22:02:09 +02:00
config CONSOLE_NE2K
bool "Network console over NE2000 compatible Ethernet adapter"
default n
help
Send coreboot debug output to a Ethernet console, it works
same way as Linux netconsole, packets are received to UDP
port 6666 on IP/MAC specified with options bellow.
Use following netcat command: nc -u -l -p 6666
config CONSOLE_NE2K_DST_MAC
depends on CONSOLE_NE2K
string "Destination MAC address of remote system"
default "00:13:d4:76:a2:ac"
help
Type in either MAC address of logging system or MAC address
of the router.
config CONSOLE_NE2K_DST_IP
depends on CONSOLE_NE2K
string "Destination IP of logging system"
default "10.0.1.27"
help
This is IP adress of the system running for example
netcat command to dump the packets.
config CONSOLE_NE2K_SRC_IP
depends on CONSOLE_NE2K
Fix some wrong capitalizations, reformat comments, fix a typo. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-23 20:29:40 +02:00
string "IP address of coreboot system"
Add support for the console over Ethernet (through PCI NE2000). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-16 22:02:09 +02:00
default "10.0.1.253"
help
Fix some wrong capitalizations, reformat comments, fix a typo. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-23 20:29:40 +02:00
This is the IP of the coreboot system
Add support for the console over Ethernet (through PCI NE2000). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-16 22:02:09 +02:00
config CONSOLE_NE2K_IO_PORT
depends on CONSOLE_NE2K
hex "NE2000 adapter fixed IO port address"
default 0xe00
help
This is the IO port address for the IO port
on the card, please select some non-conflicting region,
32 bytes of IO spaces will be used (and align on 32 bytes
boundary, qemu needs broader align)
CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-09-28 22:51:30 +02:00
config CONSOLE_CBMEM
bool "Send console output to a CBMEM buffer"
default n
help
Enable this to save the console output in a CBMEM buffer. This would
allow to see coreboot console output from Linux space.
config CONSOLE_CBMEM_BUFFER_SIZE
depends on CONSOLE_CBMEM
hex "Room allocated for console output in CBMEM"
Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-05 01:21:17 +02:00
default 0x10000
CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-09-28 22:51:30 +02:00
help
Space allocated for console output storage in CBMEM. The default
Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-05 01:21:17 +02:00
value (64K or 0x10000 bytes) is large enough to accommodate
CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-09-28 22:51:30 +02:00
even the BIOS_SPEW level.
config CONSOLE_CAR_BUFFER_SIZE
depends on CONSOLE_CBMEM
Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-05 01:21:17 +02:00
hex "Room allocated for console output in Cache as RAM"
CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-09-28 22:51:30 +02:00
default 0xc00
help
Console is used before RAM is initialized. This is the room reserved
in the DCACHE based RAM to keep console output before it can be
saved in a CBMEM buffer. 3K bytes should be enough even for the
BIOS_SPEW level.
console: add support for QEMU's debugcon Add support for sending debug output to an I/O port. It can be used together with QEMU's isa-debugcon driver to log the coreboot output to a file. The port is configurable and defaults to 0x402 which has established as the de facto standard. For example, SeaBIOS+OVMF [1] use that one too. [1] http://www.linux-kvm.org/page/OVMF Open Virtual Machine Firmware Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29 13:06:22 +02:00
console: add qemu prefix to debugcon Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30 10:32:31 +02:00
config CONSOLE_QEMU_DEBUGCON
console: add support for QEMU's debugcon Add support for sending debug output to an I/O port. It can be used together with QEMU's isa-debugcon driver to log the coreboot output to a file. The port is configurable and defaults to 0x402 which has established as the de facto standard. For example, SeaBIOS+OVMF [1] use that one too. [1] http://www.linux-kvm.org/page/OVMF Open Virtual Machine Firmware Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29 13:06:22 +02:00
bool "QEMU debug console output"
depends on BOARD_EMULATION_QEMU_X86
default y
help
Send coreboot debug output to QEMU's isa-debugcon device:
qemu-system-x86_64 \
-chardev file,id=debugcon,path=/dir/file.log \
-device isa-debugcon,iobase=0x402,chardev=debugcon
console: add qemu prefix to debugcon Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30 10:32:31 +02:00
config CONSOLE_QEMU_DEBUGCON_PORT
console: add support for QEMU's debugcon Add support for sending debug output to an I/O port. It can be used together with QEMU's isa-debugcon driver to log the coreboot output to a file. The port is configurable and defaults to 0x402 which has established as the de facto standard. For example, SeaBIOS+OVMF [1] use that one too. [1] http://www.linux-kvm.org/page/OVMF Open Virtual Machine Firmware Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29 13:06:22 +02:00
hex "QEMU debug console port"
console: add qemu prefix to debugcon Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30 10:32:31 +02:00
depends on CONSOLE_QEMU_DEBUGCON
console: add support for QEMU's debugcon Add support for sending debug output to an I/O port. It can be used together with QEMU's isa-debugcon driver to log the coreboot output to a file. The port is configurable and defaults to 0x402 which has established as the de facto standard. For example, SeaBIOS+OVMF [1] use that one too. [1] http://www.linux-kvm.org/page/OVMF Open Virtual Machine Firmware Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29 13:06:22 +02:00
default 0x402
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
choice
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
prompt "Default console log level"
default DEFAULT_CONSOLE_LOGLEVEL_8
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_8
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "8: SPEW"
help
Way too many details.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_7
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "7: DEBUG"
help
Debug-level messages.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_6
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "6: INFO"
help
Informational messages.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_5
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "5: NOTICE"
help
Normal but significant conditions.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_4
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "4: WARNING"
help
Warning conditions.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_3
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "3: ERR"
help
Error conditions.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_2
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "2: CRIT"
help
Critical conditions.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_1
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "1: ALERT"
help
Action must be taken immediately.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
config DEFAULT_CONSOLE_LOGLEVEL_0
Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8. Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 21:29:45 +02:00
bool "0: EMERG"
help
System is unusable.
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
endchoice
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
config DEFAULT_CONSOLE_LOGLEVEL
Make console maximum/default log level a choice option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 15:35:24 +02:00
int
default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
help
Map the log level config names to an integer.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
add CONFIG_NO_POST as it is used in the code, and move it together with CONFIG_SERIAL_POST Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30 11:57:28 +02:00
config NO_POST
bool "Don't show any POST codes"
default n
console: support integrated 7-segment displays for POST codes Add a configuration option POST_PORT which defaults to 0x80 and can be redefined by boards which have integrated POST displays on another I/O port. Change post.c to output POST codes to this port instead of 0x80 hardcoded. Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/221 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-18 22:54:51 +02:00
rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST because that is what it does. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 08:47:35 +01:00
config CONSOLE_POST
bool "Show POST codes on the debug console"
depends on !NO_POST
add CONFIG_NO_POST as it is used in the code, and move it together with CONFIG_SERIAL_POST Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30 11:57:28 +02:00
default n
help
If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST because that is what it does. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 08:47:35 +01:00
device) on the debug console.
add CONFIG_NO_POST as it is used in the code, and move it together with CONFIG_SERIAL_POST Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30 11:57:28 +02:00
Add support for storing POST codes in CMOS This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-10 04:09:56 +02:00
config CMOS_POST
bool "Store post codes in CMOS for debugging"
Disable CMOS_POST and IO_POST on non-PC80 systems Because they use outb instructions, they are bound to fail on non-PC80 systems like ARM. Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1974 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2012-12-06 23:25:27 +01:00
depends on !NO_POST && PC80_SYSTEM
Add support for storing POST codes in CMOS This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-10 04:09:56 +02:00
default n
help
If enabled, coreboot will store post codes in CMOS and switch between
two offsets on each boot so the last post code in the previous boot
can be retrieved. This uses 3 bytes of CMOS.
config CMOS_POST_OFFSET
hex "Offset into CMOS to store POST codes"
depends on CMOS_POST
default 0
help
If CMOS_POST is enabled then an offset into CMOS must be provided.
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
defined in the mainboard option table.
Extend CMOS POST code logging to store extra data This can be used to indicate sub-state within a POST code range which can assist in debugging BIOS hangs. For example this can be used to indicate which device is about to be initialized so if the system hangs while talking to that device it can be identified. Change-Id: I2f8155155f09fe9e242ebb7204f0b5cba3a1fa1e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58104 Reviewed-on: http://review.coreboot.org/4229 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-10 19:21:41 +02:00
config CMOS_POST_EXTRA
bool "Store extra logging info into CMOS"
depends on CMOS_POST
default n
help
This will enable extra logging of work that happens between post
codes into CMOS for debug. This uses an additional 8 bytes of CMOS.
Make POST codes written to IO port optional This adds more configurability to POST codes. The current assumption is that POST codes should be written to an IO port (e.g. LPC) if POST codes are enabled. This changes the assumption so that POST codes can be written to the serial console without being written to an IO port. This enables POST codes by default using "default y" to avoid changing current behavior. Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1685 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05 21:34:09 +01:00
config IO_POST
bool "Send POST codes to an IO port"
Disable CMOS_POST and IO_POST on non-PC80 systems Because they use outb instructions, they are bound to fail on non-PC80 systems like ARM. Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1974 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2012-12-06 23:25:27 +01:00
depends on PC80_SYSTEM
Make POST codes written to IO port optional This adds more configurability to POST codes. The current assumption is that POST codes should be written to an IO port (e.g. LPC) if POST codes are enabled. This changes the assumption so that POST codes can be written to the serial console without being written to an IO port. This enables POST codes by default using "default y" to avoid changing current behavior. Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1685 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05 21:34:09 +01:00
default y
help
If enabled, POST codes will be written to an IO port.
add CONFIG_NO_POST as it is used in the code, and move it together with CONFIG_SERIAL_POST Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30 11:57:28 +02:00
Make POST codes written to IO port optional This adds more configurability to POST codes. The current assumption is that POST codes should be written to an IO port (e.g. LPC) if POST codes are enabled. This changes the assumption so that POST codes can be written to the serial console without being written to an IO port. This enables POST codes by default using "default y" to avoid changing current behavior. Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1685 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05 21:34:09 +01:00
config IO_POST_PORT
depends on IO_POST
hex "IO port for POST codes"
default 0x80
help
POST codes on x86 are typically written to the LPC bus on port
0x80. However, it may be desireable to change the port number
depending on the presence of coprocessors/microcontrollers or if the
platform does not support IO in the conventional x86 manner.
endmenu