Make the definitions of rules compliant with
others.
Change-Id: Ieef3a9c3fae5beaa1ea3e14e890cfb9145090c3b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12685
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The former interpretation sprung from the x86 way of doing things
(assuming top-alignment to 4GB). Extend the mechanism to work with CBFS
regions residing elsewhere.
It's compatible with x86 because the default region there resides at the
old location, so things fall in place. It also makes more complex
layouts and non-x86 layouts work with negative base addresses.
Change-Id: Ibcde973d85bad5d1195d657559f527695478f46c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12683
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
At some point in the past disconnected PCIe bridges were completely
disabled to work around a hang on bridge probe. This hang was
resolved at some point, and the disconnected PCIe bridges should
be enabled to receive a bus number per the RPR.
This resolves a slew of warnings in the Linux boot log regarding
invalid bridge configurations for disconnected bridge devices.
Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12673
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
ELOG requires SPI_FLASH, so don't bother selecting if if SPI_FLASH isn't
available.
Change-Id: I080ac47e74aba820c94409d4913647abee215076
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12661
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If
used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when
it was used in the C code.
Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12664
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I6336881f0ec3568e14c03c55c7c060eba9f4be53
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12675
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
If the toolchain for a stage/architecture wasn't present, we'd call the
shell with '-v', generating an ugly warning:
/bin/sh: - : invalid option
Usage: /bin/sh [GNU long option] [option] ...
/bin/sh [GNU long option] [option] script-file ...
GNU long options:
...
Change-Id: Icd6d7a00083ee1695591ff96da36b7868be0c2f0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are
depending on it not being enabled.
Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12663
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The existing code for the Lenovo T400 works without changes on the
Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both
laptops.
Change-Id: I300408a8a0ed00476aee6061925befc2822fb505
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10545
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS)
Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present,
so just remove CPU_MICROCODE_IN_CBFS.
SMM_MODULES was removed in
commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG)
Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
QEMU can do this for a while now.
Change-Id: I3a5027a7afc9dd18463d26cb42fe68747a89f6b0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I didn't go back through the development guide for this.
But based on test, if the empty entry is filled as 0xFFFFFFFF,
instead of 0, the USB3 port can not be used.
Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant
with the case before the amdfwtool is used.
Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Kconfig symbols were missing an underscore, so were not getting
evaluated properly.
Change-Id: I619cf3f44f44f9c9699482d64164d3db28cd4c8f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12559
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It seems that no one add period in Kconfig.
Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12668
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Add a Kconfig option to set the firmware descriptor to allow EM100 use.
Change-Id: If5d7cd6ad671f0328ee5be0b5e660dbc837fcac3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until there's a reason to, don't print a warning about the missing
power8 compiler.
Change-Id: I47c60e0a16892f0fa228e1439e0424926bca00a4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12634
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The existing code incorrectly used standard PCI access
calls in the bootblock. Use the I/O PCI access calls
as the normal PCI access mechanisms have not yet been
set up.
Also ensure the recovery jumper GPIO has been set to
input mode before reading it.
Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12651
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the 3rdparty/blobs submodule to bring in the latest
CarrizoPI binaries.
Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
After several internal discussions, teams at Intel with stakes in
coreboot have decided to each assign one or more maintainers. These
maintainers can be expected to provide a point of contact for
assistance with technical (code-related) issues, testing on real
hardware, and making sure that their FSP-related areas continue to
function with upstream coreboot.
They understand that the inclusion of their information in the
MAINTAINERS file does not give them any extra power over their areas.
At the same time, nobody expects any community process to change.
The one expectation is that reasonable efforts be made to contact
these maintainers when making fundamental changes to their areas, or
when discussing code removal.
Change-Id: I7af7b37a5e3a233cc29adb20dd5bb8fa07dbdd53
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12643
Tested-by: build bot (Jenkins)
Reviewed-by: David Guckian <david.guckian@intel.com>
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE.
- CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the
default values for these new config options.
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in
commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver)
Change-Id: I97461c5e0c14075dcf8a35c96a0b0f1651e2e8e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12654
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE.
- CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the
default values for these new config options.
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in
commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver)
Change-Id: I2775c3676d5f458a4c31fe0c1d571bc2b9221a5c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
After several internal discussions, teams at Intel with stakes in
coreboot have decided to each assign one or more maintainers. These
maintainers can be expected to provide a point of contact for
assistance with technical (code-related) issues, testing on real
hardware, and making sure that their FSP-related areas continue to
function with upstream coreboot.
They understand that the inclusion of their information in the
MAINTAINERS file does not give them any extra power over their areas.
At the same time, nobody expects any community process to change.
The one expectation is that reasonable efforts be made to contact
these maintainers when making fundamental changes to their areas, or
when discussing code removal.
Change-Id: I1aa135838984973f648dec5dbb35ff73992e9289
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12644
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
The help text had gotten kind of sloppy. There was a missing newline
in the add-stage command, some of the lines were too long, etc.
Change-Id: If7bdc519ae062fb4ac6fc67e6b55af1e80eabe33
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The _HID was present for the top level BTNS and LEDS Devices, but
was missing in the individual devices.
The alternative would be to supply the GPIO being used as an _ADR
object, but since it looks like the driver already has another
method of handling that, it isn't required.
Fixes these IASL warnings:
dsdt.aml 1522: Device (BTN1)
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 1567: Device (LED1)
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 1576: Device (LED2)
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 1587: Device (LED3)
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12582
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO
were never added to the coreboot codebase when the Rangeley code was
brought in from Sage. These symbols disabled ACPI code that was unused
because it caused dmesg warnings due to conflicts with drivers trying to
claim the same addresses as the ACPI code. Because it could be used on
some other platforms, it was left in instead of being completely
removed.
- Change the Kconfig symbol names to simple #defines in the mainboard
code.
- Add the #defines along with comments to the reference platform.
- Hook everything together in dsdt.asl
- Update new mainboard littleplains the same way.
Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12552
Reviewed-by: David Guckian <david.guckian@intel.com>
Tested-by: build bot (Jenkins)
In coreboot, bool, hex, and int type symbols are ALWAYS defined.
Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The PER_DEVICE_ACPI_TABLES Kconfig symbol is no longer used as it was
removed in commit 83f81cad (acpi: Remove monolithic ACPI)
Change-Id: Ie6ba252f6e7d33da9d4500f1201367f116e4c505
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12554
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0. The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0. On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.
This issue did not affect ACPI interrupt routing.
This is just a workaround, and the root issue still needs to be fixed.
Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12630
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0. The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0. On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.
This issue did not affect ACPI interrupt routing.
This is just a workaround, and the root issue still needs to be fixed.
Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12629
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The folder southbridge/intel/common/firmware is already being included
so does not need to be added a second time here.
Change-Id: I60d795a60c772547278a5a5e0c9a023a93f90417
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12636
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Jenkins keeps failing trying to build AMDFWTOOL because it's being
built by multiple platforms at the same time. Putting it into the tools
list and having it built ahead of time should fix this problem.
Change-Id: I2a8308036135729f0ed19502f3e039aca009b3f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12647
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The microcode for the Rangeley chip is supplied as .h files in the
Rangeley FSP POSTGOLD4 package.
When the rangeley microcode gets put into the blobs directory, this
can be reverted and the binary file put into the makefile.
Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The eagleheights platform had 3 warnings:
The SIO device needs an _ADR object to specify the address in addition
to the operating region.
Not all the paths through the _OSC method returned a value. According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.
dsdt.aml 341: Device(SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 140: Method (_OSC, 4)
Warning 3115 - ^ Not all control paths return a value (_OSC)
dsdt.aml 140: Method (_OSC, 4)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _OSC)
- Remove Kconfig default disabling IASL warnings as errors.
Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12522
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Including the help targets in the list of NOCOMPILE targets means they
can run even if the toolchain is mucked up. Since they contain info on
building the toolchin, this is useful.
- Separate the three current parts of the help target into individual
components: help_coreboot, help_toolchain, and help_kconfig. This is
mostly for the help_toolchin target which will be printed out by
toolchain.inc.
Change-Id: I365d95fd63e22bddd122fb1fede6f04270e03d63
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12542
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SeaBIOS dropped support of VERSION variable and
is reproducible without it.
Change-Id: Iea1dc20e18aa5c274060e3cd55cd9e95086a602d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12645
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Make sure the build system knows how to start building the various
integrated payloads we support.
Change-Id: I2128d09c78795e0a41b055975e9f7052e3d951ee
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12641
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We don't need COREBOOT_ROM_DEPENDENCIES anymore because the dependencies
are taken care of by the cbfs-files mechanism. REFCODE_BLOB also doesn't
need to be an explicit dependency.
Change-Id: I3f32cce79683e57a174724179bc2ac59a8cdda94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12648
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
BRANCH=chromeos-2015.07
BUG=none
TEST=verified on Oak rev3
Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f
Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297224
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The config file added to CBFS is the short version created by defconfig.
The build system tried to add a header describing the version for quite
a while now, but failed because it wrote to the file, then had kconfig
overwrite it with the config data.
While at it, rely on build.h and its version information instead of
calling git manually.
Change-Id: I5e4d6c857594a55432c05bf1480973fc950f4d4a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12558
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The E38xx legacy uart fires IRQ4, not IRQ3.
PCI based IRQ A is switched from IRQ4 to IRQ3,
to get a working IRQ for the legacy uart.
Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12622
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Zheng Bao