Commit Graph

7431 Commits

Author SHA1 Message Date
Hung-Te Lin 05dccae75d cbfstool: move flat-binary parsing to cbfs-mkpayload.
The ELF parsing and payload building in add-flat-binary command should be
isolated just like mkpayload and mkstage.

Since the add-flat-binary command creates a payload in the end , move payload
processing to cbfs-mkpayload.c.

To test:
   cbfstool coreboot.rom add-flat-binary -f u-boot.bin -n fallback/payload \
	-l 0x100000 -e 0x100020

To verify, get output from "cbfstool coreboot.rom print -v":
   fallback/payload               0x73ccc0   payload      124920
   INFO:     code  (no compression, offset: 0x38, load: 0x1110000, length:..)

Change-Id: Ia7bd2e6160507c0a1e8e20bc1d08397ce9826e0d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2197
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01 06:06:41 +01:00
Hung-Te Lin 4d87d4e09b cbfstool: Add -v (verbose) output.
Add -v (verbose) to every command, and allow printing debug messages.

Revise logging and debugging functions (fprintf(stderr,...), dprintf...)
and verbose message printing with following macros:
	ERROR(xxx):	E: xxx
	WARN(xxx)	W: xxx
	LOG(xxx)	xxx
	INFO(...)	INFO: xxx  (only when runs with -v )
	DEBUG(...)	DEBUG: xxx (only when runs with more than one -v)

Example:
	cbfstool coreboot.rom print -v
	cbfstool coreboot.rom add -f file -n file -t raw -v -v

Normal output (especially for parsing) should use printf, not any of these
macros (see usage() and cbfs_locate(), cbfs_print_directory() for example).

Change-Id: I167617da1a6eea2b07075b0eb38e3c9d85ea75dc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2196
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01 05:54:24 +01:00
Martin Roth 7fb692bd86 Fam15tn: Move SPD read from mainboards into wrapper
Continuing with the mainboard cleanup for F15tn, move the functions
to read the SPD from the mainboards for Thatcher and Parmer into the
wrapper for the northbridge/amd/agesa/family15tn.

Move the SPD address customization for the mainboard into the
devicetree.cb file.

Unrelated side note - Porting.h has an un-closed #pragma pack(1)
that can cause confusing side-effects.  AGESA's structures all
use this, but coreboot's don't.  Be sure to include the coreboot
.h files BEFORE Porting.h is included, not after.

This fix has been tested.

Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2190
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
2013-02-01 04:00:02 +01:00
David Hendricks 50c0a50ac6 armv7: unify stage hand-off routines
This replaces the current stage-specific exit/entry functions with
generic versions. Now all stages compile with stage_entry(), which
is placed at .text.stage_entry.armv7, and stage_exit().

Snow's ramstage files are also updated to avoid build breakage.

Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2254
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-01 03:25:30 +01:00
Ronald G. Minnich 79e36d9060 Improve how our printk calls do_div by using constants.
The do_div code has a nice optimization in it when it is called with
constants. The current highly generalized use of it defeats those
optimizations and causes trouble on ARM, resulting in a complex and
buggy code path.

Since we only need to print in bases 8, 10, and 16, do a minor
restructuring of the code so that we call do_div with constants.
If you need base 2, print in base 16 and do it in your head. :-)

This fixes an ongoing problem with ARM, will not harm X86, and will
help PPC should we ever want to support it again.
Plus, I don't have to ever try to understand the div64 assembly and where
it's going wrong :-)

Change-Id: I6a480011916eb0834e05c5bb10909d83330fe797
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2235
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-31 23:18:16 +01:00
Ronald G. Minnich bc3abbbaf0 armv7: don't hang on divide by zero
People make mistakes. Hanging the box is not a good reason to kill the firmware,
esp. since this is probably happening in a printk.

The only issue with the recursive call to printk is that we may
deadlock if we have locked something. But we can at least try.
Hanging is certainly not what we want ...

Change-Id: Ib3bc87bc395ae89e115cf6d042f4167856422ca1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2233
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-01-30 22:36:25 +01:00
Ronald G. Minnich b7e0535862 Exynos5250: Get DDR3 working by changing what is compiled and add a function
This is a minor set of changes to get DDR3 going.

Move compilation of DDR3 startup to the romstage. Fix a prototype that
was missing a void. Remove a function that is overly flexible, and
even though it is overly flexible only actually can handle one type of
RAM. Mainboards only support one type of DRAM, so create a function
to explicitly initialize the type of DDR we have -- DDR3.

With these changes, and the previous changes, google snow is ready to run
the ramstage.

Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-30 21:39:22 +01:00
Ronald G. Minnich 21d0fc0d37 Add a clean target to the run firmware (runfw) Makefile
It's just good hygiene.

Change-Id: Ie7d4557c1d0dcf7fc015852c4c9b2eae29c4acfc
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-30 21:22:04 +01:00
Hung-Te Lin 7e494050d6 armv7: Add SPI driver for Exynos.
The SPI flash driver for Exynos chipset.

Verified to boot on snow/armv7.

Change-Id: I7eef67a9c57f825d09f13ea44c2b59b54345fa7b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2229
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 19:51:23 +01:00
Hung-Te Lin 6fe0cab205 Extend CBFS to support arbitrary ROM source media.
Summary:
	Isolate CBFS underlying I/O to board/arch-specific implementations as
	"media stream", to allow loading and booting romstage on non-x86.

	CBFS functions now all take a new "media source" parameter; use
	CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
	API Changes:
		cbfs_find => cbfs_get_file.
		cbfs_find_file => cbfs_get_file_content.
		cbfs_get_file => cbfs_get_file_content with correct type.

CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
the ROM may come from USB, UART, or SPI -- any serial devices and not available
for memory mapping.

To support these devices (and allowing CBFS to read from multiple source
at the same time), CBFS operations are now virtual-ized into "cbfs_media".  To
simplify porting existing code, every media source must support both "reading
into pre-allocated memory (read)" and "read and return an allocated buffer
(map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
provides simple memory mapping simulation.

Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
is defined for CBFS functions to automatically initialize a per-board default
media (CBFS will internally calls init_default_cbfs_media).  Also revised CBFS
function names relying on memory mapped backend (ex, "cbfs_find" => actually
loads files). Now we only have two getters:
	struct cbfs_file *entry = cbfs_get_file(media, name);
	void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);

Test results:
 - Verified to work on x86/qemu.
 - Compiles on ARM, and follow up commit will provide working SPI driver.

Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:58:32 +01:00
Steven Sherk 5fc64dca45 Rename family15 pci northbridgeops functions.
This is a port of the following
commit 8a49ac7f80

    Rename fam14 pci northbridge ops functions.

    Clarify the northbridge ops function names.

original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id7889bf02e2696220081251acdf695327267c796
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2225
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30 17:39:50 +01:00
Steven Sherk f434058b04 Rename family15tn pci northbridgeops functions.
This is a port of the following
commit 8a49ac7f80

    Rename fam14 pci northbridge ops functions.

    Clarify the northbridge ops function names.

original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icda3ec58219baa177af3b1dce729c6ad1f744be8
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2226
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30 17:37:34 +01:00
Paul Menzel e1ea5151de libpayload: Update README with Git repository URL and directory location
Change-Id: I3e068f5e6c1eb875df0885c0ce43a03082be31a5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2228
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:36:22 +01:00
Mike Loptien 58089e859d Family 14: Update for string portability.
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: I6327c9769c2544bbc56155a2f89afd767487faf6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2227
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30 17:36:10 +01:00
Stefan Reinauer cc5b344662 Project PIANO aka tianocoreboot
This is a Tiano Core loader payload based on libpayload.  It
will load a Tiano Core DXE core from an UEFI firmware volume
stored in CBFS.

Currently Tiano Core dies because it does not find all the UEFI services it needs:

coreboot-4.0-3316-gc5c9ff8-dirty Mon Jan 28 15:37:12 PST 2013 starting...
[..]
Tiano Core Loader v1.0
Copyright (C) 2013 Google Inc. All rights reserved.

Memory Map (5 entries):
  1. 0000000000000000 - 0000000000000fff [10]
  2. 0000000000001000 - 000000000009ffff [01]
  3. 00000000000c0000 - 0000000003ebffff [01]
  4. 0000000003ec0000 - 0000000003ffffff [10]
  5. 00000000ff800000 - 00000000ffffffff [02]

DXE code:  03e80000
DXE stack: 03e60000
HOB list:  03d5c000

Found UEFI firmware volume.
  GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3
  length: 0x0000000000260000

Found DXE core at 0xffc14e0c
  Section 0: .text     size=000158a0 rva=00000240 in file=000158a0/00000240 flags=60000020
  Section 1: .data     size=00006820 rva=00015ae0 in file=00006820/00015ae0 flags=c0000040
  Section 2: .reloc    size=000010a0 rva=0001c300 in file=000010a0/0001c300 flags=42000040

Jumping to DXE core at 0x3e80000
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 3E96708
HOBLIST address in DXE = 0x3E56010
Memory Allocation 0x00000003 0x3E80000 - 0x3EBFFFF
FV Hob            0xFFC14D78 - 0xFFE74D77
InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 3E95EA0
InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 3E9630C

Security Arch Protocol not present!!

CPU Arch Protocol not present!!

Metronome Arch Protocol not present!!

Timer Arch Protocol not present!!

Bds Arch Protocol not present!!

Watchdog Timer Arch Protocol not present!!

Runtime Arch Protocol not present!!

Variable Arch Protocol not present!!

Variable Write Arch Protocol not present!!

Capsule Arch Protocol not present!!

Monotonic Counter Arch Protocol not present!!

Reset Arch Protocol not present!!

Real Time Clock Arch Protocol not present!!

ASSERT_EFI_ERROR (Status = Not Found)
ASSERT /home/reinauer/svn/Tiano/edk2/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c(461): !EFI_ERROR (Status)

Change-Id: I14068e9a28ff67ab1bf03105d56dab2e8be7b230
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2154
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:34:40 +01:00
Paul Menzel 7d3c7f1089 ASRock E350M1: Remove unused variable `reg8` from `romstage.c`
[…]
        CC         romstage.inc
    src/mainboard/asrock/e350m1/romstage.c: In function 'cache_as_ram_main':
    src/mainboard/asrock/e350m1/romstage.c:48:5: warning: unused variable 'reg8' [-Wunused-variable]

This change was already done for AMD Persimmon in the following
commit.

    commit d7a696d0f2
    Author: efdesign98 <efdesign98@gmail.com>
    Date:   Thu Sep 15 15:24:26 2011 -0600

        Persimmon updates for AMD F14 rev C0

Change-Id: I8f1ae1a609b87b197583934f0556f66b64e6994d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2230
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-01-30 15:31:03 +01:00
Hung-Te Lin 5a9f45c757 cbfstool: Prevent file name to be corrupted by basename().
Calling basename(3) may modify content. We should allocate another buffer to
prevent corrupting input buffer (full file path names).

Change-Id: Ib4827f887542596feef16e7829b00444220b9922
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2203
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30 03:07:34 +01:00
Ronald G. Minnich 3414234f5a Exynos5250: change all unsigned with no type to 'unsigned int'
At some point we did a lot of cleanup to replace bare 'unsigned'
with 'unsigned int'. Do that work for this imported code as well.

At some point, we may find we can shrink these 'int's to something
smaller, thought I very much doubt it's worth the trouble.

Change-Id: Ic3da491c0188c56c836f8b9c4c8f26a31b4b3573
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2223
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 23:59:45 +01:00
Ronald G. Minnich 88e4691ed9 Exynos5250: add debug prints to DDR3 startup code.
It can be handy to have debug prints as DRAM is started up, so that
in the case of failure (does that ever happen?) you've got some
idea where it failed.

This patch adds some DEBUG_SPEW prints to the DDR3 code. I am doing this
as its own CL because we may find we want to revert it. That's unlikely
but it is not impossible if we skew the timing in some way.

This code works for some trivial DRAM tests.

Change-Id: I57e8d2a2d8df6b8ec8cd0d414681fc513e9999e3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2222
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 23:59:34 +01:00
Ronald G. Minnich 770996fd86 Exynos5250: make vendor enums in the timing array more debuggable.
The timing array is crucial to proper operation of DRAM.

Getting a valid pointer to it is hence very important. Unfortunately,
the constants chosen for the vendor were '1', and '2', (this in a
32-bit word) which in a debug print makes it almost impossible to tell
if you've got a misaligned pointer. Note: coreboot people did not
choose them :-)

So, give them values which are extremely unlikely to occur elsewhere
in the array (or in memory, for that matter).

Given the frequency with which this check occurs, i.e. once, I would
much prefer strings but I expect I'd get shouted down on that
one. Constants in this case are an almost useless optimization but
we'll go with them for now. Note no space is saved by not using
strings: there's an entire function somewhere devoted to mapping the
enum to a string!

Debug prints of pointers to structs in this array are now far more
useful than they were.

See snarky comment in the code (left there to make sure nobody gets
tempted to get fancy again). Comment now less snarky.

This is tested on google snow to the point that the DRAM works.

Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2221
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-29 23:59:24 +01:00
Hung-Te Lin 657ea6a13d cbfstool: Change "locate" output to prefix "0x".
Currently "cbfstool locate" outputs a hex number without "0x" prefix.
This makes extra step (prefix 0x, and then generate another temp file) in build
process, and may be a problem when we want to allow changing its output format
(ex, using decimal). Adding the "0x" in cbfstool itself should be better.

Change-Id: I639bb8f192a756883c9c4b2d11af6bc166c7811d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2201
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 06:08:31 +01:00
Hung-Te Lin 4505cebdad cbfstool: Remove unused header files.
cbfs-mk*.c does not work with real files / command line so header files with
file I/O and getopt can be removed.

Change-Id: I9d93152982fd4abdc98017c983dd240b81c965f5
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2200
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 04:14:43 +01:00
Ronald G. Minnich 90b4ce2775 armv7: Clean up the mmu setup a bit
The previous incarnation did not use all of mmu_setup, which meant
we did not carefully disable things before (possibly) changing them.

This code is tested and works, and it's a bit of a simplification.

Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2204
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2013-01-29 00:15:03 +01:00
David Hendricks 1fb9bfa0f9 armv7: nuke global_data.h and remove some references to gd struct
This begins to remove references to global data which u-boot used.
There are still many commented out references to gd-> and bd-> which
we'll fix once we're happy with the replacements.

Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2210
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-29 00:02:53 +01:00
David Hendricks 4a484203d0 armv7: Clean out weak symbols and unnecessary #ifdef's in cache files
This just removes unused code. If for some reason we don't want to
initialize cache, then the CPU or mainboard specific init routines
don't need to call these.

Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2209
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-29 00:02:18 +01:00
Dave Frodin 6d1708dd46 AMD/Persimmon: DP0 is connected to a LVDS connector
This change is required in order to use a LVDS panel
attached to the LVDS connector.

Change-Id: Id97c233f964151b6515bd46c797425d0e6690cbd
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2188
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-28 20:26:29 +01:00
Hung-Te Lin d173962c6e cbfstool: Store global variables into struct.
cbfstool.c uses lots of global variables for command line options and all named
as "rom*". This may be confusing when other global variables also start with
rom, ex:	int size = rom_size + romsize;
(rom_size is from command line and romsize is the size of last loaded ROM image).

If we pack all rom_* into a struct it may be more clear, ex:
	do_something(param.cbfs_name, param.size, &romsize);

Change-Id: I5a298f4d67e712f90e998bcb70f2a68b8c0db6ac
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2195
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-28 19:59:40 +01:00
Anton Kochkov dd678a2e16 msrtool: Decoding for most of Intel Core 2 MSRs
Added bits/bitfields descriptions and decoding values
into intel_core2_later.c file, which describe
MSRs for Intel processors, based on later Core 2
architecture.

Change-Id: If577c8ed944afe34f86944cc03a780fba6b3dbba
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1171
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-28 18:36:33 +01:00
Patrick Georgi d1de45e095 ioapic: Factor out counting code to `ioapic_interrupt_count`
No need to keep duplicate variants of counting ioapic interrupts.

Change-Id: I512860297309c46e05cc5379bf61479878817b1e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2185
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-27 12:21:41 +01:00
Paul Menzel dfff8a1631 AMD boards, ASRock E350M1: Remove whitespace in front of comma in DSDT
commit 585a400697
    Author: zbao <fishbaozi@gmail.com>
    Date:   Thu Apr 12 11:27:26 2012 +0800

        Leverage the Pstate table created by AGESA.

… introduced unneeded whitespace in front of a comma.

Revert that part of the above commit. In the file for AMD Dinar
tabs and spaces are mixed, but leave that alone for the beginning.

Change-Id: I279cd0cb0be8c79258034733773f2ae1c2207cce
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2187
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-01-26 19:26:30 +01:00
Olivier Langlois 70f39871a9 inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump
reference for Atom MSRs are from
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3C: System Programming Guide, Part 3
Order Number 326019, January 2013, Table 35-4, 35-5

Has been successfully tested on the targeted cpu.

Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2192
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-25 20:09:24 +01:00
Stefan Reinauer 658e4d3ea9 libpayload: use $(DOTCONFIG) instead of .config
When overriding the DOTCONFIG variable, make install
will fail in libpayload.

Change-Id: I332be3a4ca2620a32a6f5fbe683e6c71f0d6a9e9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2178
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-25 20:06:46 +01:00
Patrick Georgi 336b8b1712 AGESA: Kconfig: Drop useless depends statement
`depends on FOO` in

        if FOO
          ... depends on FOO
        endif

is useless.

Introduced in

        commit 4b508341bc
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Wed Jul 13 17:16:13 2011 -0700

            Add AMD Family 10 support to cpu folder

and probably copied later on in the following commit.

        commit d3e990c6e5
        Author: Kerry Sheh <shekairui@gmail.com>
        Date:   Tue Feb 7 20:31:35 2012 +0800

            AGESA F15: AGESA family15 model 00-0fh cpu wrapper

Change-Id: I67cf231e3047a07cb6f0eeb5f77be368674a0603
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2186
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Hengelein <ilendir@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-25 18:14:34 +01:00
Aladyshev Konstantin be0e92568f clear_ioapic: Fix reading of number of interrupts for IO-APICs
Apply the same fix for `setup_ioapic` as done in the following commit.

commit 23c046b6f1 Author: Nico Huber <nico.huber@secunet.com> Date: Mon Sep 24 10:48:43 2012 +0200

	Fix reading of number of interrupts for IO-APICs

	The number read from the io-apic register represents the index of the
	highest interrupt redirection entry, i.e. the number of interrupts
	minus one.

	Change-Id: I54c992e4ff400de24bb9fef5d82251078f92c588
	Signed-off-by: Nico Huber <nico.huber@secunet.com>
	Reviewed-on: http://review.coreboot.org/1624
	Tested-by: build bot (Jenkins)
	Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: I7b730d016a514c95c3b32aee6f31bd3d7b2c08cb
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2043
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-23 13:16:57 +01:00
Marc Jones d5c998be99 Add MMCONF resource to AMD fam14 PCI_DOMAIN.
The coreboot resource allocator doesn't respect resources
claimed in the APIC_CLUSTER. Move the MMCONF resource to the
PCI_DOMAIN to prevent overlap with PCI devices.

Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2167
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
2013-01-22 19:17:35 +01:00
Paul Menzel 5e732b8bf0 util/runfw/googlesnow.c: Remove trailing whitespace
$ git stripspace < util/runfw/googlesnow.c > /tmp/bla
    $ mv /tmp/bla util/runfw/googlesnow.c

Introduced with original commit.

    commit b867281a07
    Author: Ronald G. Minnich <rminnich@gmail.com>
    Date:   Wed Jan 16 11:59:34 2013 -0600

        Utility to run the snow bios in user mode

Change-Id: I146c07a918ef99e8ae3c0dd72cf28fae22312e43
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2183
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-22 19:04:29 +01:00
Marc Jones 8a49ac7f80 Rename fam14 pci northbridge ops functions.
Clarify the northbridge ops function names.

Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2166
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-01-22 12:18:10 +01:00
Martin Roth 73e86a88d2 F15tn: Fix all warnings, enable warnings as errors
Enable 'all warnings being treated as errors' in thatcher and parmer.

Fixed the following warnings on parmer / thatcher:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
 In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
 In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
 In function 'GetPstateGatherDataAddressAtPost':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
 In function 'MemNInitNBDataTN':
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
 warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
 warning: assignment from incompatible pointer type [enabled by default]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
 In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
 In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
 warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
 note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
 warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0:
 note: this is the location of the previous definition
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
 warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
src/include/cpu/x86/lapic_def.h:9:0: note:
 this is the location of the previous definition

In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
                 from src/mainboard/amd/parmer/mainboard.c:28:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
 warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
 note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
 warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0: note:
 this is the location of the previous definition

Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2171
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22 12:17:07 +01:00
Paul Menzel 2edf77cc29 src/lib/timestamp.c: Fix spelling of tim*e*stamp
Change-Id: I96d41882c92e577ce816264c493376d2f2d950f6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2181
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-01-22 12:15:08 +01:00
Martin Roth 80e351695f Hudson: Legacy free question is hudson only
The "system is legacy free" question accidentally escaped
from the hudson Kconfig where it was intended to stay and
went coreboot-wide.  This puts it back inside the boundries
of the hudson southbridge where it belongs.

I also commented the endif statements to make it easier to
tell where things belong.

Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2179
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22 08:52:24 +01:00
David Hendricks 35934415c4 armv7: add ARM-encoded bootblock_exit() stub
This replaces the call() function with a stub which is compiled
separately using -marm. See http://review.coreboot.org/#/c/2175/
for details.

Change-Id: I7f8c45b5e63ec97b0a82294488129d1c97ec0cbf
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2180
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-22 06:12:39 +01:00
Martin Roth f5726ea544 Hudson: Cleanup - change SB800 references to hudson
Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.

This is just cleanup and should make no functional difference.

Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-01-21 18:55:33 +01:00
Martin Roth 2892023fd4 AGESA F15tn: Move callouts into northbridge wrapper
There are currently too many things in the mainboard directories that
are really more suited to being in the northbridge / southbridge
wrappers.  This is a start at moving some of those functions down
into the wrappers.

Move the bios callback functions into the northbridge/amd/agesa/family15tn
directory from the mainboard directories.  These can still be overridden
by any mainboard just by updating the pointer in the callback table to
point to a customized version of the function.

Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:54:51 +01:00
Martin Roth e4cd00cacb Save and restore F15TN graphics command register
In the AGESA routine GfxInitSview() called in the S3save path,
the IO Space bit was getting cleared from the command register.
This kept seabios from initializing the video bios.  If the vbios
was loaded by coreboot, this routine was skipped, allowing seabios
to initialize vbios as well.  I have modified the routine to save
and restore the command register instead of clearing the IO Space
bit.

Change-Id: I756b0606adbc47da96780308c911852e39f547c7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2172
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:54:35 +01:00
Martin Roth eac220f8b5 Hudson: Changes to support agesa/hudson for legacy free
Add Kconfig option for Legacy free and hook it into the parmer
AGESA initialization as well as the FADT code. This should really
be done inside the southbridge wrapper and not in the mainboard,
but for now the code to attach it to is inside the mainboard.

Update Kconfig for parmer and thatcher to default to legacy free.

Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2157
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:54:17 +01:00
Martin Roth 0fbaf18ed4 Hudson: Changes to agesa/hudson FADT for ACPI 3.0
Update the southbridge/amd/agesa/hudson FADT generation for ACPI
3.0 compliance similar to what was done for cimx/SB800/fadt.c in
commit 9aa4389.

    commit 9aa43892e6
    Author: Martin Roth <martin@se-eng.com>
    Date:   Fri May 25 12:23:32 2012 -0600

        Update SB800 CIMX FADT

According to the datasheet, PMA_CNT_BLK is no longer available
and PM2_CNT_BLK should not be used.  Setup for these has been
removed from the table and .h file.

Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2140
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:54:05 +01:00
Martin Roth 931df3a96b F15tn / Hudson: Change SATA NumOfPorts register setting
The Number of Ports register says that it should be set to the maximum
number of ports supported by the silicon.  AGESA was setting this to be
the number of enabled ports.  If port 1 was the only port with a drive,
this value got set to 0, indicating 1 port.  This causes SeaBIOS to only
look at port 0 and quit, never finding the drive on port 1.

Dave Frodin: I also verified that this patch allows a SATA drive plugged
into port 2 to be detected without a device in port 1.

Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2165
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:53:51 +01:00
Martin Roth c89d3daf32 Parmer / Thatcher: devicetree.cb cleanup and whitespace
Re-formatting and cleaning up the devicetree.cb files for
parmer and thatcher.

Change-Id: Ic458e59701c1f2593b0a035b96cac60df476ee82
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2164
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2013-01-21 18:53:11 +01:00
Martin Roth 2d8815197e F15tn: Modify devicetree to fix S3 resume
The way that devicetree.cb was configured for the family 15tn boards
was doing... interesting things to the video device initialization.
This was causing S3 resume to fail.

There is a disconnect between how the devicetree should be configured
if there are multiple HT links on the CPU and how it's configured if
there's only one HT link.  These platforms were set up as if they
had multiple HT links, which was causing duplicate instances of
devices in the device list.

The scan for the IO Hub was removed from the northbridge code which
isn't a problem for F15tn devices.

Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2160
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:52:30 +01:00
Ronald G. Minnich b867281a07 Utility to run the snow bios in user mode
This program lets you test run a snow coreboot image in user mode
on a properly equipped arm system (usually an ARM chromebook).
This is a real time saver as you don't have to flash each time.
We've found and fixed some nasty bugs with this one.

Anyway, the instructions on how to use this are in the binary.

Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2159
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-19 18:35:31 +01:00