Commit Graph

43938 Commits

Author SHA1 Message Date
MAULIK V VAGHELA 3c0ecd57c1 soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus
coreboot always assumes that BSP APIC ID will always be 0 but as
per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can
be any processor whose index/APIC ID might not be 0.

To handle this situation, init_cpu call is required to modify to
handle dynamic detection of APIC ID from BSP instead of hardcoding
always through devicetree. Function has been updated to create
a new node with actual BSP APIC ID when devicetree doesn't contain
APIC ID defined. In case APID ID is defined, function will use a
node with the APIC ID defined in devicetree.

Changes also requires to remove "lapic 0" hardcoding from devicetree
to allow code to fill BSP APIC ID dynamically. Otherwise coreboot
will create an extra node for CPU with APIC ID 0 and it'll show as a
extra node in kernel. This will cause kernel to report wrong (extra)
core count information then actually present.

BUG=None
BRANCH=None
TEST=Boot the JSL system and observe there is no functional impacts.
Without this CL kernel core count in `lscpu` = 3
With this CL, kernel core count is corrected to 2.

Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09 06:13:07 +00:00
Ryan Chuang 43a3aa0cf4 vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/O
Disable reading of vdram/vddq/vmddr to reduce access of I2C
to reduce DRAM init time by about 30ms.
The values were only needed by HQA report and not needed on
production units.

BUG=b:195274787

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09 01:53:56 +00:00
Ryan Chuang eb94a4a6de vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM
frequency counts to reduce DRAM initialization time by about 100ms.

BUG=b:195274787

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09 01:53:29 +00:00
Rex-BC Chen 5889f02032 payloads/libpayload: add MTK_TIMER_V2 config
The timer structure (in particular, the offset to memory addresses)
on recent MTK SoCs for example MT8195 has been changed.

BUG=b:195274787

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56845
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09 01:53:20 +00:00
Rex-BC Chen 257eb1354e mb/google/cherry: Improve boot time by raising little CPU frequency
Raise little CPU to 2GHz at romstage to improve boot time by about
100 ms.

BUG=b:195274787

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id6aac8f9db86a6c1e61ea94863f2cbde12c0482e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09 01:53:06 +00:00
James Lo 55c98c368c soc/mediatek/common: add mt6359p vcore support
Add mt6359p vcore set/get support.
To adjust frequency of little core, we need to adjust voltage of vcore.

Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: Ibf49390ba78870b834c6d0b64e3f0f30f3494f18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09 01:53:00 +00:00
Wenbin Mei ca33b74acf mb/google/cherry: early-init eMMC
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, Depthcharge needs it
20ms after started) so we have to start initialization in coreboot.

BUG=b:195274787
TEST=emerge-cherry coreboot
BRANCH=cherry

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: Idc86f9121fa4a34f09a683f7a81087c13ea3dd42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09 01:52:53 +00:00
Wenbin Mei da0acc6195 mb/google/cherry: select mmc storage config
Select mmc storage config for cherry.

BUG=b:195274787
TEST=emerge-cherry coreboot
BRANCH=cherry

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I67c8795b6e6fc121e8fe61c40da05593faa02d94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09 01:52:46 +00:00
Angel Pons e72dc3d46a mb/google/auron/var/lulu: Uniformise dual-channel handling
Lulu is the only variant that does not disable channel 1 in pei_data
when the SPD index indicates it is unused. For consistency with the
other variants that use SPD files, disable channel 1 explicitly.

Change-Id: I8c613c5d90075495d2f76d33abf15d74ac63c125
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55802
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06 16:28:38 +00:00
Sunwei Li 503d93d870 mb/google/dedede/var/cappy2: Add camera support
Add camera support in devicetree and associated GPIO configuration.

BUG=b:193397569
BRANCH=dedede
TEST=Camera function is OK

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I3275ab408f6a03735a35eaa8025c36df09c9898c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-06 16:27:43 +00:00
Scott Chao 18141d8c51 ec/google/chromeec: Add code for KEY_MICMUTE and KEY_KBD_BKLIGHT_TOGGLE
- Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE.

- Sync ec_commands.h
This change syncs the coreboot version of google ec_commands.h with the
ec_commands.h from the google ec repository. This is a straight copy
except for the the copyright header.

BUG=b:194146863
BRANCH=none
TEST=check on evtest
type 4 (EV_MSC), code 4 (MSC_SCAN), value 9e
type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1

type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b
type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Ie4fa3e627f448265f72279704d258b2d3fe8fc17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06 16:26:51 +00:00
Scott Chao 3ecf50bd7a arch/x86/acpi: rename KEY_KBDILLUMTOGGLE to KEY_KBD_BKLIGHT_TOGGLE
Also change scan code from e02b to e01e. This is trying to fill the gaps in the standard table. The advise from Googler is using e01e for the keyboard backlight toggle key.

BUG=b:194146863
BRANCH=none
TEST=check on evtest

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I402192ff354f30da35aec43202df9f1407911d34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56763
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06 16:26:44 +00:00
Idwer Vollering d78af11f72 util/kconfig: detect ncurses on FreeBSD
Even though pkg-config might be installed, it might or will not return
true in the checks whether 'PKG' or 'PKG2' is installed.

Extend the script to look in another location for ncurses.h

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-06 15:35:39 +00:00
Rex-BC Chen eef442d0c1 soc/mediatek/mt8192: initialize DFD
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I39a4391c1d1e832d77b709f8f899bb1c6dcacd69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-06 14:43:02 +00:00
Angel Pons 59c9327cbd mb/prodrive/hermes: Update HDA codec subvendor ID
Tested on prodrive/hermes.

Change-Id: I72be8bde59d9eb0c1eff8c65dc734c6805732e09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56086
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06 14:42:10 +00:00
Karthikeyan Ramasubramanian 953f2adb18 soc/amd/common/block/spi: Enable host burst to 4 DWORD when using DMA
Disabling the 4 DWORD bursts causes SPI DMA operations to stall, so
leave it enabled when SPI DMA is used.

BUG=b:194919326
TEST=Build and boot to OS in Guybrush.

Change-Id: I363acdcdb4178a10e4f7eb2bbcbd6d0ca7924f2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-08-05 22:59:05 +00:00
Felix Held 90ac882a32 soc/amd/common/block/spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
Add a new Kconfig option to enable or disable the 4 DWORD burst support
of the SPI controller and use this setting to determine if the
corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or
cleared. Since fch_spi_disable_4dw_burst can now enable or disable the
feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the
SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit
definition in the SPIx2C SPI100 Host Prefetch Config register in the
public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig
option.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-08-05 22:58:33 +00:00
Ricardo Quesada c2cf3946c9 util/elogtool: add tool to print elog events
Add a new tool that that prints elog events.
The tool, as input, accepts either a file with the RW_ELOG contents, or
if the file is not provided it reads the contents of RW_ELOG by calling
the "flashrom" tool.

The tool is based on "mosys eventlog list"[1]. For the moment it only
supports "list", but future commits will add additional functionality.

This commit also adds missing ELOG defines needed for the tool. These
defines are added with the rest of the ELOG defines, in
include/commonlib/bsd/elog.h

The tool is placed inside util/cbfstool. The rationale behind the
decision, is that this tool shares a lot in common with the other tools
located in cbfstool: vboot dependency, shared files like common.o and
valstr.o, and in spirit is similar to some of the tools located in
cbfstool/.

As an example, you call the tool like the following:

$ elogtool list -f rw_elog_dump.bin

[1]: https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/lib/eventlog/elog.c

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1fe1c9ed3c4c6bda846055d4b10943b54463935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-08-05 22:00:35 +00:00
Ricardo Quesada cb4bb393b5 Move ELOG defines/struct to commonib/bsd/elog.h
Move ELOG defines and structs from include/elog.h to
include/comonlib/bsd/elog.h.

This is needed because the will be used from util/
(in a future commit).

It also replaces uNN types with uintNN_t types, for the reason described
above.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: I4f307f599a311810df2367b7c888f650cff1214a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05 15:55:27 +00:00
Bora Guvendik 3198848dfa soc/intel/alderlake: Add GFx Device ID 0x46aa
This CL adds support for new ADL-M graphics Device ID 0x46aa.

TEST=boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib24b494b0eedad447f3b2a3d1d80c9941680c25d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05 15:55:20 +00:00
Anil Kumar 9b73c2b2f4 mb/intel/adlrvp: Add probed fw_configs to SMBIOS OEM strings
This feature was added in ADL-M RVP for discovering correct
audio topology using OEM string e.g., "ADL_MAX98373_ALC5682I_I2S"
for discovering boards having audio expansion card

Bug=None
Test= With CBI FW_CONFIG set to 0x100

localhost /home/root # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
        String 1: ADL_MAX98373_ALC5682I_I2S

Change-Id: I05887d9d654eae6d9d2da731d8ab4cf4a05c287f
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 15:55:12 +00:00
Bora Guvendik 70a815a1e0 mb/intel/adlrvp_m: Enable SaGv support
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I80f11b8f0c2a1fdccbc322c3c4783c61684ff37a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55634
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 15:55:08 +00:00
Scott Chao 6db97a31ef mb/google/brya/variants/gimble: add TcssAuxOri
Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping.
Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages.

BUG=b:195087071
BRANCH=none
TEST=check both orientation can output display on type-c monitor.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05 15:55:04 +00:00
Jason Glenesk 2cdcc254c8 mb/amd/majolica:Enable IOMMU Device for majolica
Enable IOMMU PCIe device.

BUG=b:194173037
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631

Cq-Depend: chrome-internal:4027293,4027294
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ia84276ca98163158d818a0efc3e021b93ab365de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05 15:55:00 +00:00
Jason Glenesk 0834d86c1f soc/amd/cezanne/fsp_m_params:Configure the iommu_support UPD
Configure the IOMMU support upd if iommu is enabled.

BUG=b:194173037

Cq-Depend: chrome-internal:4027293,4027294
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I56b433cdc1ca5459c51b4b764e22292bd27b8892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05 15:54:54 +00:00
Jason Glenesk 8d35428331 soc/amd/cezanne: Generate IVRS for cezanne
Generate IVRS for cezanne using common IVRS generation code.

BUG=b:190515051
TEST=Build cezanne coreboot image. Compare IVRS table with agesa
generated tables.

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05 15:54:50 +00:00
Jason Glenesk f934fae032 soc/amd/picasso: Move IVRS generation code to common
Move IVRS acpi table generation code to common, so that it can be shared
by other programs.

BUG=b:190515051
TEST=Build picasso coreboot image. Compare IVRS tables before/after
change.

Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05 15:54:47 +00:00
Raymond Chung 3fc0190bbc mb/google/dedede: Create bugzzy variant
Create the bugzzy variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:192521391
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BUGZZY

Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 15:46:12 +00:00
Casper Chang 946d73490a mb/google/brya/variants/primus: enable PS2 interface
BUG=b:187969783

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1e063524cfa4121c38cfed23e95557953511d884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05 15:45:12 +00:00
Patrick Georgi 4b8b2a0f0b util/kconfig: Provide default for DEFCONFIG
Our documentation claims that the DEFCONFIG make variable, used for
targets such as savedefconfig, defaults to 'defconfig'.
With the update to kconfig 5.13 we lost this default, so bring it back.

Fixes: 53ea1d44f0 ("util/kconfig: Uprev to Linux 5.13's kconfig")
Resolves: https://ticket.coreboot.org/issues/317
Change-Id: Idb88b69ffa855fa97df8c821601308e717575550
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56718
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 02:48:56 +00:00
Julius Werner 763db46ccd MAINTAINERS: Update vboot maintainers
Add current maintainers for vboot-related code, and combine the vboot
and vboot2 sections which are not really separate anymore. What's left
in vendorcode/google/chromeos isn't really related to vboot anymore
since the vboot code was moved under src/security, so take it out of
there.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I59a2df9c1580291a6d29537868aab0e1b339a2ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-04 19:46:18 +00:00
Scott Chao f2be7d6056 mb/google/brya/variants/gimble: Remove DPTF fan control
BUG=b:195378817
BRANCH=none
TEST=Check fan is able to control by EC

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I84c020e470194072bb796f75f8a1304832504469
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56768
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:55:55 +00:00
Ren Kuo 163dfe68f6 mb/google/dedede/var/magolor: Modify SSFC for camera and touchscreen
The all shipped magolor and maglia has SSFC= 0x840.
The value is defined as 5M MIPI camera.But the value:0x840 will
conflict with the updated touchscreen field.
It will cause some touchscreen no function if make auto-update new
firmware.The CL would correct the field error.

The original fields:
CAMERA_WFC 38 40
TS_SOURCE  41 44

Correct fields:
MIPI Cam
  CAMERA_WFC 38 40
  CAMERA_UFC 41 42
  CAMERA_VCM 43 44
Touch-screen
  TS_SOURCE  45 48

The SSFC value of Magolor:
CAMERA_OVTI5675  5M AF (SSFC = 0x840)
CAMERA_OVTI8856  8M AF (SSFC = 0x880)

BUG=b:194639170
TEST=Build firmware and verify on camera and touch-screen devices

Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56685
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:16:09 +00:00
Aamir Bohra 9fe70ed197 mb/amd/bilby: Add support for HDMI display
DDI 0/1 ports are shared for DP and HDMI. This implementation
adds support for HDMI display when HDMI is set as connector type
in ddi descriptors.

TEST=verify display over HDMI(0 and 1) in OS.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: I9697211c556f12d1fc0d49418b227fbe6b342673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04 15:16:05 +00:00
Paul Menzel 9e34060d52 acpi/acpigen_ps2_keyb: Align comments using tabs
Fixes: ffd80fd2 ("arch/x86/acpi: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLE")
Change-Id: I2cca8cdbbd3607acca88da7b273ca6b080db9e7c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:16:02 +00:00
Mark Hsieh f41da47d34 mb/google/brya/variants/gimble: Update overridetree for gimble
According to the schematic diagram of proto, added drivers/i2c/max98390 to device ref i2c0 and deleted device ref hda.

BUG=b:191811888
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I0f0a8c84db3fbc963797d11246c5d31b395bb744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:15:59 +00:00
Ricardo Quesada d45e70c124 Move elog_internal.h to commonlib/bsd/include
Move elog_internal.h to commonlib/bsd/include/bsd/.
And rename it from elog_internal.h to elog.h.

Since this file will be included from util/ it also converts the "uNN"
types into "uintNN_t" types.

The two defines that are not used by util/ are moved to
drivers/elog/elog.c, the only file that includes them.

Move also the function elog_verify_header() from drivers/elog/, to
commonlib/bsd/elog.c since this function will be called from util/
as well.

The rationale behind moving elog's defines & structs to
commonlib/bsd/include is to make them available to util/ tools and/or
payloads (should it be needed in the future).

The files that are being relicensed to BSD were coded by Duncan Laurie,
and he is Ok with the relicense.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:15:55 +00:00
Ricardo Quesada 470ca5714f Move post_codes.h to commonlib/console/
Move post_codes.h from include/console to
commonlib/include/commonlib/console.

This is because post_codes.h is needed by code from util/
(util/ code in different commit).

Also, it sorts the #include statements in the files that were
modified.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:15:51 +00:00
Aamir Bohra 1b9ae18726 mb/amd/bilby: Enable DP2 and DP3 enumeration
DP2 and DP2 is muxed with USBC port. This implementation
configures mux for DP functioanlity.

TEST=Verify display over DP2 and DP3.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: If0c8dfbb47175789bb27d4506c1e8b45c425c76a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04 15:15:48 +00:00
Nico Huber 12441dce06 console/hw-debug_sink: Update for fast/slow console distinction
Change-Id: I9ac110c7b812f912f0f87cbe4aa218d4a78e6aaf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:45 +00:00
Nico Huber 234e7ecb29 soc/intel/cannonlake: Allow to configure maximum package C state
Sometimes it's preferable or even necessary (e.g. stability issues) to
limit the maximum package C state. Let's add a devicetree option that
keeps the current behavior if it is left unset.

Change-Id: I0dc254d34f46de4c65cb85cc92e4b7f26618888d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:42 +00:00
Nico Huber e4bc55b843 soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is given
Change-Id: I4f9b62fd944d8a91d53bc584c88797f23de1e5ca
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-04 15:15:39 +00:00
Nico Huber 6ac8a9f826 soc/intel/cannonlake/vr_config: Print configured values
These values are quite important and our default tables sometimes have
holes. We should at least make it visible what the resulting settings
are.

Change-Id: Ic716d073da1c2638c4b16f2eac01b83a0768d22f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:35 +00:00
Nico Huber b06d847ea9 soc/intel/cannonlake/vr_config: Add TDC values for CFL-H 6+2
Values were taken from PDG (571391), 51.3 IMVP8 Voltage and Current
Requirements.

Change-Id: Iffa29386cb7da333353dafd0ba3a61ca61a0ccac
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:32 +00:00
Nina Wu c25aa5b47e soc/mediatek/mt8195: Add devapc basic drivers
Add basic devapc (device access permission control) drivers.

DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.

1. Initialize devapc.
2. Set master domain and secure side band.
3. Set domain remap.
4. Set default permission.

Change-Id: I3677657a117caed0d73526f78b0ebe8180148335
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-04 09:23:45 +00:00
Shelley Chen 530624de21 3rdparty/qc_blobs: Uprev to new HEAD (98db386)
Now that gsi_fw blob has landed, need to uprev the qc_blobs.

Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 23:40:01 +00:00
Thejaswani Putta 8239d076bf mb/google/brya: Add RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 6 and provide the reset GPIO / src clk pins.

BUG=None
BRANCH=None
TEST=Build and boot the coreboot image, check if device is enumerated
in the lspci list after warm/cold reboot cycles, run suspend cycles and
check if WWAN is entering L2 LPM.

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-03 21:47:05 +00:00
Vinod Polimera e8cd480046 sc7180: Add display support for mipi panels
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels.
- add simple rm69299 panel as an example to append new mipi panels.
- use existing edid struct to update mipi panel parameters.
- add dsi command tx interface for mipi panel on commands.

Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 21:22:26 +00:00
Scott Chao 8ca68cf2ae mb/google/brya/variants/primus: configure correct type-c port
BUG=b:195274799
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4abf7b2d98b188735ef79f8ffbee4c02099ec021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56583
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 20:50:45 +00:00
Sean Rhodes bc35bed18e soc/intel/*: Allow configuring 8254 timer via CMOS
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-03 15:21:04 +00:00