Provide clean separation for PCI and PNP headers,
followup will also move PNP outside <arch/io.h>.
Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A default is a build-time static value, fallback. Return
value does not depend of input parameter.
Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31679
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the bus parameter, we do not use it.
It would still be possible to do per-bus selection
by evaluating the bus number, but currently we do
not have need for that either.
Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Having different signatures for the PCI config accessors
prevents them from having the same name in different
stages.
For now, work around this using __SIMPLE_DEVICE__.
Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
As we are running ACPI v3.0, references to older
than v3.0 are removed.
Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, the OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
environment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.
Though there is a way to discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.
Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fix up the logic of when to include VBOOT2_WORK symbols on x86,
which are only needed when VBOOT_STARTS_IN_BOOTBLOCK is enabled.
Also correct the value of the __PRE_RAM__ macro in the case that
VBOOT_STARTS_IN_ROMSTAGE is selected. In this case, DRAM is
already up and verstage should not be considered pre-ram.
BUG=b:124141368, b:124192753
TEST=Build locally for eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/31541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current implementation was designed for x86_32, so don't
attempt to compile it on x86_64 until it is fixed.
Fixes compilation error on x86_64.
Change-Id: Ibd87dc2979f6d45a988119c06c5f9e61b3e86171
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
To make PCI driver side arch-agnostic, function
declarations have to be in symmetrical header
file locations.
From the driver side, the correct file to include
is now <device/pci_ops.h>
Change-Id: I8076a4867fd7472beaae0a021dcf0d9c7c905871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is expected that method of accessing PCI configuration
register space via memory-mapped region is arch-agnostic.
Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are defined for __SIMPLE_DEVICE__ when PCI
enumeration has not happened yet. These should not
really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge
being located on bus 2 and available for configuration, so
I rather leave the code unchanged. Just move these out of
arch/io.h because they cause build failures if one attempts
to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to
avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having SYSTEM_TYPE_DETACHABLE and SYSTEM_TYPE_TABLET use
PM_MOBILE have them use PM_TABLET instead.
Change-Id: If0ce51e522d36420ecd5b51bdfec6cca11c00333
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These are more common system types and in some cases it is important
to know when a device is a convertible or a tablet or detachable
instead of just a laptop.
This change will select the appropriate SMBIOS enclosure type based
on the selected system type.
This is important for the Intel Virtual Button driver as it does a
check on the SMBIOS enclosure type and only enables the tablet mode
events if it is set to convertible:
https://patchwork.kernel.org/patch/10236253/
Change-Id: I148ec2329a1dd38ad55c60ba277a514c66376fcc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ACPI spec has an asl example for _PLD in the form:
Name (_PLD, Package (0x01) { ToPLD (PLD_Revision = 0x2) })
When I ported this to acpigen and diffed the results I noticed that
the binary blob was no longer provided within a package. The ACPI
spec (section 6.1.8 in version 6.2) defines _PLD as "a variable-length
Package containing a list of Buffers". This commit changes
acpigen_write_pld to use a package (the one existing caller I found
isn't wrapping the result in a package so it doesn't look like
it was intended for the callers of acpigen_write_pld to be responsible
for using a package.
BUG=none
BRANCH=none
TEST=Verified that after this change a package is use and the result
of acpigen matches what was used in the original asl.
Change-Id: Ie2db63c976100109bfe976553e52565fb2d2d9df
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If an acpi_dp table has children but no properties then acpi_dp_write()
will write out a properties UUID and package that contains no properties.
The existing function will avoid writing out a UUID and empty package
when no children exist, but it seems to assume that properties will
always be used. With this change properties are handled in a manner
akin to children so that a UUID and package are only written if
properties exist.
BUG=none
BRANCH=none
TEST=Confirmed that prior to this change a UUID and empty package was
present for a device that had children but no properties. Verified that
after this change the UUID and empty package are no longer present but
the child UUID and package are still present.
Change-Id: I6f5597713a1e91ca26b409f36b3ff9eb90a010af
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The allocation is not required before romstage,
so it can be just another CAR_GLOBAL instead of
polluting the linker script.
Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31191
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The structure is placed inside CBMEM, one should
use types with fixed size. Seems we prefer to
prepare for 64-bit builds even for MMIO pointers.
Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We need sizeof(struct ehci_dbg_info) of 88 but only
reserved 64 bytes. If usbdebug_hw_init() was called
late in romstage, for some builds it would corrupt
CAR_GLOBALs like console_inited variable and stop
logging anything.
Also change pointer initialisation such that
glob_dbg_info will hit garbage collection for
PRE_RAM stages.
Change-Id: Ib49fca781e55619179aa8888e2d859560e050876
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When rmodule is loaded CPU stack alignment is only guaranteed
to 4kiB. Implementation of cpu_info() requires that each
CPU sees its stack aligned to CONFIG_STACK_SIZE.
Add one spare CPU for the stack reserve, such that alignment can
be enforced runtime.
Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26302
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used to check romcc-built bootblock and romstage
agree about the location of 16-bit entrypoint. There was
no need to customize it as bootblock size requirement did
not grow. Just check for a fixed location at 4 GiB - 4 KiB.
With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol
for the purpose, since it appears in the same compilation
unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes.
Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Clearing the EBDA was introduced with b4aaaa "Prepare the BIOS data
areas before device init." which states that the purpose of setting up
these area's is just to make sure they are sane. On the S3 path doing
this is not needed and can even thrash data set up by payloads (mostly
SeaBIOS) that used that memory.
Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
PCI_ADDR() is tightly coupled with different setup_resource_map()
variants so move the declaration away from global namespace.
In the implementation of setup_resource_map() use the bottom
12 bits as the register mask like the other variants do already.
Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Build with TSC_CONSTANT_RATE must fail when this function
is not implemented for the platform. Weak implementation
causes division by zero in timer_monotonic_get() and
turns udelay() into no delay.
Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the
romstage.
This is useful for cbfs access in pre-CAR environments.
Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Have same usage of registers with romcc bootblock
and C_ENVIRONMENT_BOOTBLOCK.
Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The EHCI hardware needs to be initialized only once during CAR stages.
Some exception need to be made when a blob messes with the EHCI
hardware. To achieve this add a fixed location in the car.ld linker
script such that the ehci debug information can be shared across CAR
stages.
Currently this means only romstage and bootblock, but verstage can
also be hooked up later on.
Tested on google/peppy: Both the bootblock and the romstage properly
output console.
Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Also remove global ramstage-y += get_bus_conf.c, this is
specific to amdfam10.
Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Definitions of these types are arch-agnostic. Shared device
subsystem files cannot include arch/pci_ops.h for ARM
and arch/io.h for x86.
Change-Id: I6a3deea676308e2dc703b5e06558b05235191044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t is deprecated.
Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30047
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add symbols for the non C_ENVIRONMENT_BOOTBLOCK builds
and use them for stack guards.
Change-Id: Ib622eacb161d9a110d35a7d6979d1b601503b6f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The same file was replicated three times for certain
soc/intel bootblocks, yet there are no indications or need to do
chipset-specific initialisation.
There is no harm in storing the TSC values in MMX registers
even when they would not be used.
Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
