Commit Graph

4821 Commits

Author SHA1 Message Date
Myles Watson 1c0c6372a9 Fix amdk8_util.asl and explain behaviour a bit.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21 20:36:47 +00:00
Myles Watson 8d96ed4336 Get rid of this warning:
src/cpu/amd/model_10xxx/fidvid.c:758:
	warning: 'fid_max' may be used uninitialized in this function

Quoting Marc:

It [fid_max] should be initialized to 0. The !nb_cof_vid_update would mean that
the fidmax shouldn't change so the value isn't important, but 0 would be the
safest if there is another hole in the logic and CPUs are not matched.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21 17:15:55 +00:00
Myles Watson c25cc11ae3 Use lists instead of arrays for resources in devices to reduce memory usage.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21 14:33:48 +00:00
Patrick Georgi c5b87c8f89 Move generation of mptable entries for ISA to generic code.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-20 15:28:19 +00:00
Nathan Williams 1a169d2a46 Add support for the Traverse Technologies Geos mainboard.
This board is similar to the AMD Norwich mainboard.

Signed-off-by: Nathan Williams <nathan@traverse.com.au>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-20 07:35:17 +00:00
Joe Korty 6d77252e74 Move the 'USE CMOS' Kconfig question.
Move the 'USE CMOS' question from the top level to the
General Setup section of Kconfig.

Signed-off-by: Joe Korty <joe.Korty@ccur.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-19 18:41:15 +00:00
Stefan Reinauer 1c3c0faabc cosmetic comment changes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-19 18:39:23 +00:00
Stefan Reinauer ace2dc3ac1 The AMD Fam10 code breaks with coreboot 4.5.0.
Potentially caused by reordering. Going back to 4.4.4 which is known working on
Fam10 until gcc or the Fam10 code is fixed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-19 10:01:37 +00:00
Patrick Georgi 5b0280fb14 Fix path for mingw workaround. Trivial.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-19 07:21:31 +00:00
Stefan Reinauer bb33fbeb91 get rid of some duplicate inclusion warnings.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-18 16:24:07 +00:00
Stefan Reinauer 5f1ad89020 New buildgcc version.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-17 11:02:25 +00:00
Stefan Reinauer 119c58910c drop old patches from crossgcc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-17 10:21:10 +00:00
Peter Stuge b1180b42af msrtool: Print hex values using only as many digits as the field needs
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-17 07:40:20 +00:00
Peter Stuge 87964864ae msrtool: Remove some unneeded casts
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-17 07:29:47 +00:00
Rudolf Marek 417e66baa5 Sorry for this for second time. Now compile tested for both cases ;)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 22:32:58 +00:00
Rudolf Marek fdddce3b92 Sorry for this. I fixed that reverting the change for ROMCC.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 22:26:25 +00:00
Rudolf Marek beba99045c Following patch reworks car_disable into C. Tested, works here. I compared
also the GCC generated code and it looks all right. Please test on some
multicore CPU.

I added the "memory" clobber to read_cr0 / write_cr0 function as it is in Linux
Kernel. Seems that if this is missing, GCC is too smart and messes the order
of reads/writes to CR0 (not tested if really a problem here, but be safe for
future users of this function  ;) 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 21:51:34 +00:00
Rudolf Marek 4bb368cc73 Part of 5560 Dunno why I need extra delete after move.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 15:34:02 +00:00
Rudolf Marek d9c2549333 Following patch reprograms SIL3114 into PCI IDE native mode compatible class code allowing
legacy software to recognize it as IDE and boot from it. I think
this should be the default for two Tyan boards (k8s aka s2882 and s2881).

Rename the directory to sil prefix to match the Linux kernel naming.
(And I think it was a SiliconSystems wish to be named sil ;)

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 15:31:53 +00:00
Stefan Reinauer 7cfa7f97a1 Add support for the Getac P470
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 14:24:41 +00:00
Stefan Reinauer 09e0c49f36 v2 -> v4
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 14:22:43 +00:00
Stefan Reinauer 9e7a5d4359 Add two new superios to coreboot:
- SMSC FDC37n972
- SMSC SIO10N268

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 14:08:32 +00:00
Stefan Reinauer 23f703464a Add TI PCI 7412 support.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-16 13:07:59 +00:00
Anders Jenbo 96d8fef5d2 ITE IT8671F: Add it8671f_48mhz_clkin().
This fixes serial console on GIGABYTE GA-6BXE.

Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 21:29:08 +00:00
Anders Jenbo 9d1c76f54c Add initial support for the GIGABYTE GA-6BXE.
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 19:50:11 +00:00
Stefan Reinauer 2f4b7f6cb1 clean up some prototypes
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 19:11:44 +00:00
Stefan Reinauer bf264e940e i945:
* fix some potential compiler issues with newer gccs
* add some more comments
* make 32bit accesses for feature test functions
* make some objects drivers because they contain a pci_driver struct.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 19:09:20 +00:00
Stefan Reinauer cbac4981be more acpica fixes... The tricky part is the stuff in the AMD mainboard directories.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 17:15:57 +00:00
Stefan Reinauer 86d72782c7 Fix i945 ACPI for ASL Optimizing Compiler version 20100428.
The values are overwritten on the fly but without the patch iasl will refuse to
compile the code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 16:44:45 +00:00
Uwe Hermann 4bdd6438f8 Various superiotool fixes.
- IT8671F/IT8687R:

    - Fix typo: Parallel port register 0x60 value is 0x03 (not 0x01).
  
    - Fix typo: APC register 0xf6 is 0x00.
  
    - Drop register 0x07 (LDN 0 / none), that's not useful and not listed in
      any of the other Super I/Os either, it always contains the LDN number
      selected "last time", which is useless.
    
    - Fix indentation and other cosmetics.
  
  - Cosmetics, and consistency fixes in LDN names of various Super I/Os.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 16:40:55 +00:00
Patrick Georgi c928a295b3 Remove another set of includes from Fam10 romstages:
northbridge/amd/amdht/ht_wrapper.c
northbridge/amd/amdfam10/raminit_amdmct.c
cpu/amd/model_10xxx/fidvid.c
pc80/mc146818rtc_early.c

They are now included by the fam10 chipset code that requires them.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 11:02:56 +00:00
Nils Jacobs 930d32ba87 fix SeaBIOS loading on GX2.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:59:59 +00:00
Stefan Reinauer aa567a795e Fix warning. Hardware tested and didn't change behavior.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:56:46 +00:00
Nils Jacobs dd6ad3447b license header fixes
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:48:05 +00:00
Nils Jacobs 1e211327fb This patch cleanes up the Wyse S50 port and unifies the memmory regions
with Geode LX , adds gpl2 headers plus some white space fixes.

This is build and boot tested.(of course vsa loading is stil not fixed,it now
runs forever with :"Oops, exception 13 while executing option
rom")

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:45:29 +00:00
Stefan Reinauer 841af5e01e Change real mode API to allow passing intXX number or entry point and
some register values from C. 

This theoretically fixes non-vga option roms, but it also allows to use
the same assembler code for option roms and vsm.
It will also make using the bootsplash without yabel a lot easier.

Factor out and improve BDA setup, do some rom segment setup for those
option roms that need it. 

Don't call the coreboot exception handler if an exception occurs in real
mode. It's only partly usable, but mainly the Kontron 986LCD-M (and other
i945GM boards) choke on an exception #6 (invalid opcode). This particular
issue is not introduced by the changes in this patch but has been around
for quite a while at least.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-11 15:39:20 +00:00
Myles Watson 48beb82769 Make show_all_routes work for fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-10 19:45:45 +00:00
Myles Watson b904d7bce9 High tables don't have to be on node 0 on K8. Make it less restrictive.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-10 19:38:59 +00:00
Patrick Georgi 5ec3ead6dc Remove extra NULL #define in amdht code. The
common one is enough. Trivial

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 21:44:52 +00:00
Patrick Georgi 3d5bb236aa Move includes to where they are needed. This allows to simplify
romstage.c files in mainboards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 21:15:13 +00:00
Patrick Georgi bf9e5384d7 Remove pc80/serial.c includes in ROMCC boards and include
it centrally in console/console.h instead.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 21:09:58 +00:00
Anton Kochkov 7b5df5a445 Begin implementation support to IT8512/IT8513
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 15:30:45 +00:00
Stefan Reinauer 29d3a92e15 i82830: fix debugging output and clarify bracketing
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 15:15:08 +00:00
Anders Jenbo 14db1c0c6b Add registers for the it8671f chip.
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 23:28:33 +00:00
Stefan Reinauer cee5f7d996 autoprobe apic cluster and application processors on K8 systems
(fixes #18)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 22:02:54 +00:00
Nils Jacobs d37ce2e28e Add the Wyse S50 thin client to Coreboot.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 21:50:31 +00:00
Stefan Reinauer 133887d540 wipe some old unused code, this has been cleaned up now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 18:14:50 +00:00
Stefan Reinauer c53d1f3415 Patrick Georgi wrote:
Given that this is exclusively used for checking for mingw and cygwin
(both support this), at most this requires routing the error message to
/dev/null.

And rename the variable so it's not used for any non-windows purpose.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 17:15:36 +00:00
Patrick Georgi 2196a0a47a Slightly improve detecting Windows. Trivial
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 15:50:44 +00:00
Stefan Reinauer 67ee3e612f We didn't have console.initobj.o before, but the same hard coded
build rule is needed as for console.o

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 11:17:24 +00:00