Commit Graph

50490 Commits

Author SHA1 Message Date
Bo-Chen Chen 35693c5028 soc/mediatek/mt8188: Add support for MIPI panel
We need to add DSI and MIPI_TX settings to support MIPI panel.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:58 +00:00
Bo-Chen Chen bb4c9ca2d6 soc/mediatek: Fix DSI register definition for MT8186
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.

BUG=b:244208960
TEST=build pass
BRANCH=corsola

Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:37 +00:00
Bo-Chen Chen b1e7adeca1 soc/mediatek/mt8188: Add display data path for MIPI output
For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.

BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.

Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:00 +00:00
Arthur Heymans f9679c4287 nb/intel/gm45: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:23:37 +00:00
Arthur Heymans 31ba9356b8 nb/intel/i945: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:23:13 +00:00
Arthur Heymans 803029685f nb/intel/x4x: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:22:39 +00:00
Arthur Heymans 98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:22:12 +00:00
Matt DeVillier 6f573217a0 mb/google/zork: Select VBOOT by default
Zork boards will not boot without PSP verstage/VBOOT, so select it
by default.

Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69763
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:19:56 +00:00
Arthur Heymans 759448893c soc/nvidia/tegra210: Fix flushing SPI fifo
This will avoid clearing the other bits in fifo_status.

Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05 14:19:03 +00:00
Dinesh Gehlot e29dcdcdd8 soc/intel/meteorlake: Add timestamp for cse_fw_sync
The patch adds timestamp around cse_fw_sync().

BUG=none
TEST=Verified on rex, cbmem -t:

948:starting CSE firmware sync 	1,340,551 (50,657)
949:finished CSE firmware sync 	1,379,348 (38,797)

Port of 'commit b647e35119 ("soc/intel/alderlake: Add timestamp
for cse_fw_sync")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 11:33:12 +00:00
Subrata Banik cd6a45029e mb/google/rex: Add PCIe based SD controller
This patch adds PCIe based SD controller at RP 7 (from RP 11) with
Proto 1 schematics dated 11/30.

Additionally, added the RTD3 entries for the SD controller.

Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in
bootblock and SD_PERST_L (GPP_D02) is configured in romstage to
meet the power cycle requirement.

BUG=b:242917011
TEST=Able to build and boot Google/Rex. SD card detection is due
for the Proto 1 hardware.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-03 07:34:55 +00:00
Subrata Banik 8ca7d26626 mb/google/rex: Drop `board_id` check while configuring GPIO
This patch drops the usage of reading `board_id()` while performing
the GPIO configuration.

The reason to drop the board_id check is to ensure that GPIO
configuration for MLB (mainboard) would remain the same and the only
GPIO PIN configuration that differs would be due to usage of having
different DBs (daughter board) which will be taken care using
CBI (and fw_config.c file) in coreboot.

Additionally, drop unused early GPIO default configuration table.

BUG=b:260804656
TEST=Able to perform the GPIO configuration and able to boot
Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-03 07:34:34 +00:00
Subrata Banik db59e48870 mb/google/rex: Add probed fw_configs to SMBIOS OEM strings
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.

TEST=With CBI FW_CONFIG field set to 0x1561

localhost ~ # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
	String 1: AUDIO-MAX98357_ALC5682I_I2S
	String 2: CELLULAR-CELLULAR_PCIE
	String 3: UFC-UFC_MIPI
	String 4: WFC-WFC_MIPI
	String 5: DB_SD-SD_GL9755S

Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03 07:34:11 +00:00
Shelley Chen e233fc7ac1 mb/google/herobrine: NVMe id determined by logical (not physical) bit
NVMe is determined by a logical bit 1, not the physical SKU pin.
Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has
NVMe enabled on it.  Previously, I thought that it was tied to a
physical pin, but this is not correct.

BUG=b:254281839
BRANCH=None
TEST=flash and boot on villager and make sure that NVMe is not
     initialized in coreboot.

Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03 01:04:20 +00:00
Sridhar Siricilla dddaeed4c1 soc/intel/alderlake: Update cpu and pch tracehub modes
The patch gets the cpu and pch's tracehub mode from the debug area
of the Descriptor Region and updates the respective UPDs.

TEST=Build, verify the tracehub mode values.

Update CPU' and PCH's Trace Hub modes:
	img=coreboot.rom
	printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc
	printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc

Check coreboot logs:
    [DEBUG]  rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-02 18:01:06 +00:00
Tim Crawford 8e3787eaf0 mb/system76/tgl-h: Convert oryp8 to a variant
Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 15:53:49 +00:00
Jonathon Hall def33cc5bb mb/purism/librem_14: Enable both lanes of left side USB 3.0 port
Fixes using USB-C devices in either orientation on left-side USB-C
port.

Test: Plug USB-C device in both orientations on left-side USB-C port,
check speed with lsusb -t.

Change-Id: I9fbc53bb51a5225e92b0b6bb9ced87a0ab90c9ce
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69702
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:49:13 +00:00
Eran Mitrani 13e151f31c soc/intel/alderlake: skip external buses for D-states list
The devices in the list that was introduced in commit c66ea98577
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)

BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02 14:48:37 +00:00
David Wu 50a3265017 mb/google/brya/var/zydron: Add WiFi SAR table
Add WiFi SAR table for zydron.

BUG=b:260770999
TEST=build FW and checked SAR table can load by WiFi driver.

Change-Id: I8d5f966c7af3ac6d9923d4f6c851bfb340f31fab
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02 14:48:02 +00:00
Lean Sheng Tan e98dd0aad8 mb/prodrive/atlas: Enable GPP_B14 buzzer support
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required
for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using
8254 timer counter 2 output. However when 8254 timer is used, S0ix
will not work as 8254 has to be gated instead. For further info on
s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified
Checklist).

This CL also disables s0ix because it is not required by the
platform.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:47:36 +00:00
Lean Sheng Tan 998fdc06cb mb/prodrive/atlas: Add DP++ support
Update VBT configurations for DP++ and DP dongles support.

Tested working on customer's side.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7aa34297a10bf16b9043140bff91fd3a8c4009d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:46:39 +00:00
Lean Sheng Tan 08596f50b7 3rdparty/fsp: Update submodule pointer to latest master
Here are the FSP updates with latest master:
- IoT EHL MR5
- IoT ADL-P MR2
- IoT ADL-S MR3
- IoT ADL-PS PV
- IoT TGL MR7

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If4a76fe25c7b7a2c34e5bb284418c01c77b22abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70153
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:45:57 +00:00
Kapil Porwal 96c605f39a soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function
This patch refactors the `pmc_lockdown_cfg()` to remove the helper
functions and uses the `setbits32` function to enforce bit locking
as applicable.

This patch also locks PMC features like:
1. Debug mode configuration and host read access to PMC XRAM.
2. PMC soft strap message interface.
3. PMC static function.
and then calls into the PMC IPC function that informs about PCI
enumeration.

Port of -
1. commit 2eec87a553 ("soc/intel/alderlake: Refactor
`pmc_lockdown_cfg` function")
2. commit bae4a0b5a1 ("soc/intel/alderlake: Implement PMC
feature lock")
3. commit c2570dc998 ("soc/intel/alderlake: Implement PMC
soft strap interface lock")
4. commit f021952c40 ("soc/intel/alderlake: Implement PMC
static function lock")
5. commit 4578914153 ("soc/intel/alderlake: Call into PMC
IPC to inform PCI enumeration done")

BUG=none
TEST=Boot to OS on google/rex.

Register values in OS -
# busybox devmem 0xfe0018d4 32 #bit31
0x80000000
# busybox devmem 0xfe001024 32 #bit21,18,17,4
0x00362610
# busybox devmem 0xfe001818 32 #bit27,22
0x2B4F0004
# busybox devmem 0xfe00104c 32 #bit0
0x00000001


Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:45:23 +00:00
Elyes Haouas a521d66116 nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock
Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02 14:44:41 +00:00
Elyes Haouas 5a845ee894 nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'
'gpu_lvds_use_spread_spectrum_clock'is only used on i945.

Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:40:22 +00:00
Elyes Haouas dc3beea75d sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02 14:39:56 +00:00
Elyes Haouas 87a98b55b2 nb/intel/pineview: Use {true,false} instead of {0,1}
"use_crt" and "use_lvds" are boolean, so use "true/false".

Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:33:16 +00:00
Tim Crawford 976050113e mb/system76/adl-p: Disable SATA DevSlp
After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in
system76/ec@cc3effb6a4 ("board/system76/common: use SLP_S0# pin for
modern standby detection"), DevSlp blocks suspend entry. Disable it
until it is fixed.

Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 14:30:51 +00:00
Tim Crawford fa2c118af4 mb/system76/adl-p: Add Galago Pro 6 as a variant
The Galago Pro 6 (galp6) is an Alder Lake-P board.

Tested with a custom edk2 UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- All USB ports
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-1087-gde016a17

Not working:

- Detection of devices in TBT slot on boot

Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 14:30:25 +00:00
Tim Crawford 5b7b04c938 mb/system76/cml-u: Convert lemp9 to a variant
Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 14:29:53 +00:00
Martin Roth 1ef3779516 mb/google/herobrine: Update FMD file for multiple ROM sizes
The Piglin & Hoglin boards were built with a couple of different sizes
of ROM chips.  Despite this, the desire was to use just a single FMD
file.  The different sizes are already accounted for in Kconfig, so
add the Kconfig size here to be used.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02 14:29:11 +00:00
Patrick Georgi 3d4b1710eb kconfig2html: Denote that the script is python3
`python` as a command isn't universally available anymore after the
python2/python3 drama.

Change-Id: I9d68873d86dc3f044238d921c10fc434a83a76f5
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02 08:34:14 +00:00
Patrick Georgi a6dedb8c22 board-status: Implement handling of "Clone of"
Change-Id: Ifb728ebb5d0e98b0c8a59f3bd8803ce193a05e5f
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02 08:34:01 +00:00
Patrick Georgi 52941673b1 board-status: Remove shell version, update docs
Change-Id: I532db49799eadf3214a70297c5fc84aa006bc3f7
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02 08:33:54 +00:00
Subrata Banik b955304869 soc/intel/meteorlake: Allow sending late EOP cmd to CSE
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.

BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time

Without this patch:

942:before sending EOP to ME	1,795,702 (354)
943:after sending EOP to ME	1,950,526 (154,824)

With this patch:

942:before sending EOP to ME	2,051,406 (35,484)
943:after sending EOP to ME	2,057,583 (6,177)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:52:07 +00:00
Subrata Banik adbef6d2b3 soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.

Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.

BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-12-02 07:51:58 +00:00
Subrata Banik 17a3da8b99 soc/intel/cmn/cse: API to perform essential CSE operations post EOP
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.

Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.

BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:51:52 +00:00
Subrata Banik 5214c4091f soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()`
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.

This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.

1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations

Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.

BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:51:42 +00:00
Subrata Banik bed82b0c40 soc/intel/cmn/cse: Create another config for sending CSE EOP cmd late
Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.

1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.

During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).

Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.

The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.

Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.

The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.

BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:51:36 +00:00
Felix Singer 52191f2123 util/crossgcc/buildgcc: Disable LLVM_INCLUDE_{TESTS,EXAMPLES}
Building of LLVM tests and examples is enabled by default, but they are
not necessary. Thus disable them.

Change-Id: I58b09e276967e97856da65e5876b27f0bae3f0cc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-02 06:54:05 +00:00
Felix Singer f8157af3aa util/crossgcc/buildgcc: Use one line per configure option
To improve the readability and visibility of the configure options, move
each of them to a separate line.

Change-Id: Ifc39e4d0849d220d85e1d9ce92fc008fec610694
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-02 06:53:40 +00:00
Felix Singer 3e7438b001 util/crossgcc/buildgcc: Put configure option before target dir
Change-Id: If1b724f9c9b4d2a8ce166946794c1c0882ad1653
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-02 06:53:00 +00:00
Wisley Chen 7b1e7c30a7 mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
Adjust scl_lcnt, scl_hcnt, sda_hold value for I2C5 to meet
touchpad SPEC.

BUG=b:260540852
BRANCH=firmware-brya-14505.B
TEST=build, checked TP function work normally,
and measure the timing meet SPEC
tLOW  ~1.72 us
tHIGH ~0.63 us
tHD   ~0.69 us
fscl  383 kHz

Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-02 05:16:51 +00:00
Lawrence Chang cab2c53e3c mb/google/nissa/var/xivu: Fine-tune eMMC DLL
Fine-tune eMMC DLL based on Xivu EVT system.

BUG=b:256538132
TEST=executed 3000 cycles of cold boot successfully

Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 03:11:41 +00:00
John Su 69cab3a044 mb/google/skyrim/var/frostflow: Enable DPTC support
Enable DPTC support for frostflow.

BUG=b:257187831
TEST=emerge-skyrim coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 01:49:12 +00:00
Nicholas Chin 9eab93168d util/kconfig/README.md: Add notes about adding a new quilt patch
The patches for kconfig need to be in a format compatible with the quilt
tool, and usually also contain a header with some additional info like
the git commit. This header is in the same format as patches produced by
`git format-patch`, but the diff style git uses is incompatible with
quilt and there does not seem to be a straightforward way to format the
diff section to work.

Add some documentation for a method I found to go from a git commit to a
quilt compatible patch with git headers.

Change-Id: I7a8bbe41e0864be1d28116742b6b8b3fc440cc31
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-01 22:12:29 +00:00
Jakub Czapiga a7f669049d vboot: Allow for comparison of hash without zero-padding
Adjust asserts to allow to store and compare (at S3 resume) hashes
without padding to maximum hash length / slot size.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01 22:12:16 +00:00
Jakub Czapiga d27fff5923 vboot/vboot_common: Fix vboot_save_data() code exclusion guard
Compilers are not optimizing-out code correctly. This patch fixes
incorrect behavior by splitting if statement and extracting code to
another function, this allowing for better code size optimization and
reduction of undefined references.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-01 22:12:10 +00:00
Raymond Chung 3e6abc98d5 mb/google/brya/var/gaelin: Configure audio in devicetree
Refer to brask board to add audio settings for gaelin.

BUG=b:253177160
BRANCH=firmware-brya-14505.B
TEST=Able to verify audio playback on gaelin with kernel v5.10.

Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01 20:14:12 +00:00
Raymond Chung 7c9753c8ce mb/google/brya/var/gaelin: Add camera module settings
Modify USB2.0 port[4] settings to support camera.

BUG=b:238252678
BRANCH=firmware-brya-14505.B
TEST=with brask overlay changes, camera in camera app works

Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01 20:13:51 +00:00