Commit Graph

43196 Commits

Author SHA1 Message Date
Angel Pons 9cddae151a mb/*: Specify type of `MAINBOARD_DIR` once
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.

Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:04:45 +00:00
Angel Pons ac90f593f8 src/*: Specify type of `CBFS_SIZE` once
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.

Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:02:57 +00:00
Angel Pons ac44f87465 mb/intel/galileo: Clean up `FMDFILE` Kconfig handling
Remove redundant type, prompt and help text, and replace `depends on`
clause with conditional default to allow specifying a FMAP when vboot
is not selected.

Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:02:43 +00:00
Angel Pons 5b44e7dce3 mb/facebook/monolith: Don't override `CBFS_SIZE` prompt
Change-Id: I6fac40918f1ca3227ff68e79fcae039a26356d0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56550
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:01:56 +00:00
Felix Singer 4c426262d7 mb/google/brya: Deduplicate chipset lockdown config
Due to an issue in sconfig, move `chipset_lockdown` out of
`common_soc_config` and configure it separately in the baseboard's
devicetree since it might get overwritten if a variant configures
`common_soc_config`.

Also, deduplicate the configuration of `chipset_lockdown`.

Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 12:22:47 +00:00
Felix Singer 32ca3ac9ab mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOT
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.

Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 12:21:26 +00:00
Jakub Czapiga ca3aa52cf8 tests: Add lib/libgcc-test test case
Add tests for src/lib/libgcc.c __clzsi2() implementation. Unlike GCC
implementation, coreboot one can handle zero input.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3f46071d0921e8c5edc5df3c296d11c77de01c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:32:43 +00:00
Raul E Rangel ca0606e04f arch/x86,lib/thread: Enable thread support in romstage
This change does the following:
* Pushes the cpu_info struct into the top of the stack (just like
  c_start.S). This is required so the cpu_info function works correctly.

* Adds the thread.c to the romstage build.

I only enabled this for romstage since I haven't done any tests in other
stages, but in theory it should work for other stages.

BUG=b:179699789
TEST=Boot guybrush with threads enabled in romstage

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e32e1c54dea0d0c85dd6d6753147099aa54b9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:30:48 +00:00
Raul E Rangel e279d90d4d arch/x86,cpu/x86/mp_init: Switch cpu_info index type to size_t
The alignment for `struct cpu_info` is wrong on x86_64. c_start.S uses
the `push` instruction when setting up the cpu_info struct. This
instruction will push 8 bytes but `unsigned int` is 4 bytes. By making
it a `size_t` we get the correct size for both x86_32 and x86_64.

BUG=b:179699789
TEST=Boot guybrush to the OS

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ef311aaa8333ccf8a5b3f1f0e852bb26777671c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:30:36 +00:00
Raul E Rangel 474781b270 arch/{arm,ppc64,riscv}: Remove cpu_info
The structure and function are not currently used or implemented. x86 is
the only arch that currently implements it. It is currently used for
COOP_MULTITASKING and mp_init.

Keeping around the unused definitions leads to confusion.

BUG=b:179699789
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0775ef03168f7f9c41b1b05cb8f12724d0458ba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:29:16 +00:00
Raul E Rangel a2d83c68a3 lib/thread,lib/hardwaremain: Lazy initialize threads
By lazy initializing the threads, if a stage doesn't use them, they will
be garbage collected.

BUG=b:179699789
TEST=Boot guybrush to the OS and verify threads worked

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7208ffb5dcda63d916bc6cfdea28d92a62435da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56532
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 07:28:33 +00:00
Raul E Rangel 7db7ee984c lib/thread,arch/x86: Move thread stacks into C bss
There is no reason this needs to be done in asm. It also allows
different stages to use threads. If threads are no used in a specific
stage, the compiler will garbage collect the space.

BUG=b:179699789
TEST=Boot guybrush to the OS

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5a84a62fdc75db8ef0358ae16ff69c20cbafd5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56531
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 07:28:08 +00:00
Aseda Aboagye b9d94ecd78 vboot/secdata_tpm: Add WRITE_STCLEAR attr to RW ARB spaces
It can be nice to update the TPM firmware without having to clear the
TPM owner.  However, in order to do so would require platformHierarchy
to be enabled which would leave the kernel antirollback space a bit
vulnerable.  To protect the kernel antirollback space from being written
to by the OS, we can use the WriteLock command.  In order to do so we
need to add the WRITE_STCLEAR TPM attribute.

This commit adds the WRITE_STCLEAR TPM attribute to the rw antirollback
spaces.  This includes the kernel antirollback space along with the MRC
space.  When an STCLEAR attribute is set, this indicates that the TPM
object will need to be reloaded after any TPM Startup (CLEAR).

BUG=b:186029006
BRANCH=None
TEST=Build and flash a chromebook with no kernel antirollback space set
up, boot to Chrome OS, run `tpm_manager_client get_space_info
--index=0x1007` and verify that the WRITE_STCLEAR attribute is present.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I3181b4c18acd908e924ad858b677e891312423fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56358
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 07:27:48 +00:00
Karthikeyan Ramasubramanian ce79ceec86 mb/google/dedede: Program VCCIO selection for EN_SPKR GPIO
Realtek speaker amplifiers under auto mode operation have Absolute Max
Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker
amplifier and program the VCCIOSEL accordingly.

BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.

Change-Id: Ifa0b272c23bc70d9b0b23f9cc9222d875cd24921
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26 05:31:52 +00:00
Karthikeyan Ramasubramanian 16f2c5082c soc/intel/jasperlake: Enable support to program VCCIO selection
Jasperlake is one of the few SoCs that support programmable VCCIO
selection and this support is used by Dedede mainboard.

BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.

Change-Id: I54def27a499ccba7fd25cab1048fdca06dbc535f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56536
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:30:59 +00:00
Karthikeyan Ramasubramanian 4c569b52f6 soc/intel/common/block/gpio: Add support to program VCCIO selection
Some of the Intel SoCs with more than 2 PAD configuration registers
support programming VCCIO selection. Add a pad configuration macro to
program VCCIO selection when the GPIO is an output pin.

BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.

Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:30:48 +00:00
Alex1 Kao 9b6a3a0370 mb/google/dedede/var/pirika: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for pirika.

BUG=192601233
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26 05:24:08 +00:00
Arthur Heymans a1509d4545 soc/nvidia/tegra124: Increase bootblock size
Verstage even fits in 44K so one can comfortably increase the
bootblock size. This is need for the followup patches that turn
console methods into drivers, which increase the bootblock a little,
but still too much for the the bootblock to fit in the alloted size on
this platform.

Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:05:41 +00:00
Sunwei Li 7aeb1e627c mb/google/dedede/var/cappy2: Generate SPD ID for supported memory parts
Add supported memory 'K4U6E3S4AA-MGCR' for cappy2

BUG=None
TEST=Build the cappy2 board.

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ie76a4dca607bb2c3261bbe5478209a43e8430591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26 05:04:02 +00:00
Angel Pons 0eb3216489 mb/asus/p5ql-em: Add default value for `gfx_uma_size`
Taken from Asus P5QPL-AM.

Change-Id: If26e98eba5d762d99991bfc06cad1b84e1f430e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56562
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:02:25 +00:00
Ben Kao 6eb5253451 soc/intel/jasperlake: Set xHCI LFPS period sampling off time
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.

The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.

BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26 05:00:51 +00:00
Zhuohao Lee 3b28ab098e mb/google/brya: move the common config to the baseboard
This patch moves the common config to the Kconfig under
BOARD_GOOGLE_BASEBOARD_BRYA and removes the redundant config.

BUG=b:191472401
BRANCH=None
TEST=build pass

Change-Id: Ie59299dfaba6bb23758d4a4c22a6dbbb4ba6520e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56387
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 04:58:20 +00:00
Sugnan Prabhu S 22618d9f07 mb/google/brya: Enable BT offload conditionally
Currently, BT offload is disabled/enabled unconditionally based on the
devicetree settings. BT offload uses I2S lines and cannot be enabled
when a I2S based audio daughter card is active. So we need to enable
BT offload only while using soundwire based audio daugther card.

BUG=b:175701262
TEST=Verified BT offload on brya with soundwire audio daughter card
BT offload enabled

Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-26 04:50:11 +00:00
Karthikeyan Ramasubramanian b3af9f8d2e soc/amd/common/block/pm: Add support for Modern Standby event logging
Log the GPE and PM1 wake events into the event log using the SMI handler
platform callback.

BUG=b:186792595, b:186800045
TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are
logged into the event logs.
5 | 2021-07-15 16:26:43 | S0ix Enter
6 | 2021-07-15 16:26:49 | S0ix Exit
7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22   <- Trackpad
8 | 2021-07-15 16:27:07 | S0ix Enter
9 | 2021-07-15 16:27:13 | S0ix Exit
10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0
25 | 2021-07-15 16:38:13 | S0ix Enter
26 | 2021-07-15 16:38:17 | S0ix Exit
27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint

Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26 04:43:53 +00:00
Karthikeyan Ramasubramanian 589ac69850 soc/amd/common/block/acpi: Extract event logging helpers
Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.

BUG=None
TEST=Build and boot to OS in Guybrush.

Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-26 04:42:54 +00:00
Raul E Rangel 9adf4a6656 lib/thread: Add asserts around stack size and alignment
`cpu_info()` requires that stacks be STACK_SIZE aligned and a power of 2.

BUG=b:179699789
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I615623f05bfbe2861dcefe5cae66899aec306ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26 04:40:29 +00:00
Raul E Rangel 8c892070e9 lib/thread: Guard thread_run_until with ENV_RAMSTAGE
thread_run_until is a ramstage specific API. This change guards the API
by checking ENV_RAMSTAGE.

BUG=b:179699789
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4784942070fd352a48c349f3b65f5a299abf2800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56529
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 04:38:14 +00:00
Angel Pons 2f04e03e06 mb/razer/blade_stealth_kbl/Kconfig: Fix up indentation
Change-Id: I0ffae7408f11f4f517204a0a670845c11b3601a8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56549
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-25 08:51:14 +00:00
Ravi Kumar Bokka 6668ae3677 sc7280: Increased CBFS_MCACHE size
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-25 05:06:59 +00:00
Felix Held f070253659 soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bit
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-25 01:14:40 +00:00
Matt Papageorge 5a2feeda39 soc/amd/*/chip.h: Correct PSPP Enum Value
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.

BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.

Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-24 19:49:45 +00:00
Martin Roth 8baa9dfe1e mb/google/guybrush: Update GPIOs settings
- The WWAN card was being disabled later than desired.
- The SD card was never being placed into reset on BoardID 1.
- Enable Touchscreen power
- Enable PCIe_RST1 at the same points as PCIe_RST
- Remove Redundant Bootblock settings

BUG=b:193036827
TEST=Build & Boot, look at GPIO states through boot process

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-24 17:22:21 +00:00
Nikolai Vyssotski 3c3d2cf77f src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 72 to 76. Instead of checking for exact length check
reported header length against known minimum length for a given FSP
version.

BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24 15:18:43 +00:00
Subrata Banik 9bf4293c3f include/cpu: Remove one space from bitfield macro definition
This change is to maintain parity with other macro declarations.

Change-Id: I67bf78884adf6bd7faa5bb3afa2c17262c89b770
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24 11:14:08 +00:00
Subrata Banik 25429c06c3 include/cpu: Use tab instead of space
Change-Id: I025c20cbcfcfafddbd72b18bca36165b98db8220
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56548
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24 11:13:56 +00:00
Subrata Banik 39b53d9622 soc/intel/common/block: Add space before comment delimiter
Update comment section to add space before comment delimiter to
follow coding style.

Change-Id: I883aeaa9839fa96fd7baf0c771b394409b18ddca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24 11:13:41 +00:00
Shelley Chen eeaf569257 3rdparty/qc_blobs: Uprev to new HEAD (e96cde2)
Now that cpucp blobs have landed, need to uprev the qc_blobs.

Change-Id: I62dc410cee7baf5efa5c0406f35ee05a535f49b1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-24 05:37:23 +00:00
Felix Held 0b707b9180 soc/amd/common/block/cpu/mca/mca_common: remove additional newline
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-24 00:45:20 +00:00
Felix Held 9a98fc9d1d soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fch
Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 18:03:24 +00:00
Felix Held f66e781336 soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fch
Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 18:03:15 +00:00
Felix Held a754aa6d29 soc/amd/picasso/fch: make sb_clk_output_48Mhz static
sb_clk_output_48Mhz is only used in fch.c where it is also implemented,
so no need to have it visible outside of that compilation unit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 18:03:04 +00:00
Ravi Kumar Bokka 12184db008 herobrine: get boardid from GPIO configuration
Getting boardid information for the different SKU variants

BUG=b:182963902, b:193807794
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-23 17:21:07 +00:00
Patrick Georgi 1cfb599992 build system: Deduplicate symbols in objdump
New binutils versions automatically resolve references to debug symbol
files and parse their content as well when objdump'ing data. This leads
to multiple mentions of symbols, so deduplicate references.

Change-Id: I5d597399c515904313ba36d7aab9178bc0dade14
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-23 15:06:56 +00:00
Werner Zeh eac687cc36 mb/siemens/mc_ehl1: Add GPIO configuration
Provide a valid GPIO configuration based on the mainboard wiring.

Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 13:18:52 +00:00
Werner Zeh 8c4c572bc6 mb/siemens/mc_ehl1: Remove SD-Card card detect GPIO in devicetree
Since there is no SD card interface on this mainboard do not set the
card detect GPIO.

Change-Id: Ibe6799c5c540538f97d1726ec16e79f3edbb16fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56489
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 13:18:43 +00:00
Werner Zeh e8fc8f31b4 mb/siemens/mc_apl{1,2,3,5,6}: Use PCI_ALLOW_BUS_MASTER_ANY_DEVICE
Use the Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE instead of
PCI_ALLOW_BUS_MASTER to enable PCIe bus master bit as requested in
CB:56441 during review.

Change-Id: I433dbae0d9b15e41d1d0750298868341ce3d6b46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-23 13:18:27 +00:00
Werner Zeh 35e1fca8f2 drivers/intel/i210: Set PCI bus master bit only if allowed
Set the bus master bit only if the global Kconfig switch
PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit
is needed for i210 because of some old OS drivers that do not set it
and won't work properly without it.

Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-23 13:18:14 +00:00
Florian Laufenböck e85b6de804 mainboard/up/squared: Add one more DRAM configuration
Add a new configuration option with more density for
8GB variants of the up squared board.
Settings are taken from slimbootloader.

Signed-off-by: Florian Laufenböck <florian@laufenbock.de>
Change-Id: I217b04be94e913b75e2bac0a4ae1c43f2411a044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-07-23 13:17:49 +00:00
Nico Huber dee281d03f drivers/pc80/rtc: Make use of alt-century byte configurable
This legacy alt-century byte sits amidst CMOS and conflicts many option
tables. It usually has no meaning to the hardware and needs to be main-
tained manually. Let's disable its usage by default if the CMOS option
table is enabled.

Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-23 11:05:30 +00:00
Patrick Georgi 4df5779ba9 mb/google/veyron: Remove references to EC firmware board names
Chrome EC is relatively quick with retiring "old" boards from their
tree so when upreving it, the last veyron in that list that wasn't
commented out is gone as well.

Change-Id: Ie1ef693c8d0947396ee01e5aa5f40ef36c8a317a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56430
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 10:31:48 +00:00