In order to support wake from D3cold, most devices require extra
circuitry and possibly out-of-band communications to the host.
Therefore, assume that most SPI peripherals that do have wake
capabilities support wake from D3hot rather than D3cold.
This also allows coreboot to expose a power resource to perform power
sequencing for a SPI peripheral that is intended to retain power in
S3/S0ix.
If support for a device with d3cold wake support is needed, it could be
added in later as an option.
BUG=b:187228954
TEST=compile
Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The DA7219 does not support wake from D3cold, therefore update the
return value of _S0W from D3cold to D3hot.
BUG=b:187228954
TEST=compile
Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move elog_internal.h to commonlib/bsd/include/bsd/.
And rename it from elog_internal.h to elog.h.
Since this file will be included from util/ it also converts the "uNN"
types into "uintNN_t" types.
The two defines that are not used by util/ are moved to
drivers/elog/elog.c, the only file that includes them.
Move also the function elog_verify_header() from drivers/elog/, to
commonlib/bsd/elog.c since this function will be called from util/
as well.
The rationale behind moving elog's defines & structs to
commonlib/bsd/include is to make them available to util/ tools and/or
payloads (should it be needed in the future).
The files that are being relicensed to BSD were coded by Duncan Laurie,
and he is Ok with the relicense.
BUG=b:172210863
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 72 to 76. Instead of checking for exact length check
reported header length against known minimum length for a given FSP
version.
BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the bus master bit only if the global Kconfig switch
PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit
is needed for i210 because of some old OS drivers that do not set it
and won't work properly without it.
Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This legacy alt-century byte sits amidst CMOS and conflicts many option
tables. It usually has no meaning to the hardware and needs to be main-
tained manually. Let's disable its usage by default if the CMOS option
table is enabled.
Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Update proper number of sectors info for winbond W25Q512NW-IM chip
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I12a22321bb9180e32cd47faa6ac3960ba5b2dfb8
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56038
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Define new configs for Opregion versions.
2. Assign RVDA to relative address of the Opregion buffer
in case of opregion 2.1+.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)
BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A regular assignment works just as well and also allows type-checking.
It also avoids a common mistake where `sizeof` is applied to a pointer
to obtain the size of the data it points to, without dereferencing it.
Found-by: Coverity CID 1458231
Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since initial_lapicid() returns an unsigned int, change the type of the
local variables the return value gets assigned to to unsigned int as
well if applicable. Also change the printk format strings for printing
the variable's contents to %u where it was %d before.
Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit ce0e2a0140 which was
originally introduced as a workaround for the bug that the Linux kernel
doesn't know what to do with type 16 memory region in the e820 table
where CBMEM resides and disallowed accessing it. After depthcharge was
patched to mark the type 16 region as a normal reserved region, the
Linux kernel now can access the BERT region and print BERT errors. When
SeaBIOS was used as payload it already marked the memory region
correctly, so it already worked in that case.
After commit 8c3a8df102 that removed the
usage of the BERT memory region reserved by the FSP driver by the AMD
Picasso and Cezanne SoCs and made them use CBMEM for the BERT region,
no other SoC code uses this functionality. The Intel Alderlake and
Tigerlake SoCs put the BERT region in CBMEM and never used this reserved
memory region and the change for the Intel server CPU to use this was
abandoned and never landed in upstream coreboot. AMD Stoneyridge is the
only other SoC/chipset that selects ACPI_BERT, but since it doesn't
select or use the FSP driver, it also won't be affected by this change.
TEST=Behavior of the BERT code doesn't change on Mandolin
Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, we get PLD information from USB port structure itself, so
devicetree does not need to fill PLD structure anymore. Thus remove
obsolete variable.
Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since TBT controller can have maximum 2 ports per controller, our
code will loop over DFP structure twice and determine port number.
Retimer driver used to assign port number as below:
1. Check if power GPIO is assigned for particular DFP entry or not
2. If entry is there, assign loop count as port number
Since loop count is 2, retimer will never assign port number = 2
even if it's present. In case of more than 1 controller, port number
assigned will still be 0 or 1 even though actual port index might
be 2 or 3. This will create an issue where even if you do transaction
on device on controller 2 (port index 2 or 3), EC will route it on
port 0 or 1 due to incorrect port index.
Update the driver flow as per below to handle this scenario:
1. Check if power GPIO is assigned for particular DFP entry or not
2. Get USB port number from config since it's stored in usb port
information under devicetree
3. Pass the port number to ACPI SSDT and EC code
Above changes will ensure that we're assigning correct port
number as per calculation and EC will use correct port index.
BUG=b:189476816
BRANCH=None
TEST=Checked that retimer firmware update works on both ports and update
happens on correct port index.
Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create a separate function to get PLD information from USB device.
This is helpful in retimer driver where we can attach same USB
port information to retimer instance and we can avoid duplication
of information.
BUG=None
BRANCH=None
TEST=Check if code compiles and function returns correct value
Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This message is not an error, but just informational.
BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently the flow for opregion init is as below:
1. Allocate memory for opregion first (cbmem_add(opregion))
2. Check if VBT size > 6 KiB (this requires extended VBT support)
3. In case of extended VBT requirement, we allocate another chunk
of memory which is equal to size of VBT (cbmem_add(extended_vbt))
4. Pass physical address pointer to OS via RVDA
We can optimize the above flow to allocate single chunk of memory by
checking VBT size in earlier step. The new optimized flow for opregion
init is as below:
1. Check if VBT size > 6 KiB (this requires extended VBT support)
2. In case of extended VBT requirement, total memory to be allocated
is calculated as sizeof(opregion) + sizeof (extended_vbt)
In case where VBT size is < 6 KiB, total memory requirement would
be equal to sizeof(opregion)
3. Based on above calculation, allocate single chunk of memory based on
total size.
This will also be helpful for the case of virtualization where guest
users don't have access to physical address and when it needs relative
address of VBT compared to absolute address.
In case of opregion 2.1 spec, we need to pass relative address of
VBT from opregion base in RVDA. This optimization will help in meeting
this requirement since relative address of extended VBT is easy to get.
This change will ensure that it meets opregion specification
requirement and will be compatible with future versions as well.
BUG=b:190019970
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.
Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This adds OEM variables feature under DPTF as per BWG doc #541817. Using
this, platform vendors can expose an array of OEM-specific values as OEM
variables to be used in determining DPTF policy. These are obtained via
the ODVP method, and then simply exposed under sysfs. In addition, these
gets updated when a notification is received or when the DPTF policy is
changed by userspace.
BRANCH=None
BUG=b:187253038
TEST=Built and tested on dedede board
Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Now that the refactoring is complete, the unions for the table header
are no longer needed. Therefore, drop them.
Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Introduce the `smbios_full_table_len` function to consolidate table
length calculation. The case where the length of a table equals the
length of the structure happens when a table has no strings.
Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Factor out some boilerplate code into a helper `smbios_carve_table`
function, which zeroes out the table memory and fills in the header
fields common to all tables.
Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
All SMBIOS `type X` tables start with the same 4-byte header. Add a
struct definition for it, and use it where applicable. The union is
temporary and allows doing the necessary changes in smaller commits.
Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Where applicable, use the size of the associated variable.
Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Where applicable, use the size of the associated variable.
Change-Id: Icf4f1c8fe9f54c44b041a65eb46d6ec9f9fd6367
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
gpio_num is used to indicate the GPIO which is taken from gpio_soc_defs.h file.
Support for dynamic generation of ASL file for Camera was added for JSL
when there were less than 256 GPIOs. ADL now has more GPIOs and therefore
uint8_t is not enough any more
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I0a5fdb612c8cf689d356af8591b9ad101360c25d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55538
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FSP_ARRAY_LOAD macro for checking and loading
array type configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes unnecessary __packed attribute from the structure
defined in chip.h
BUG=None
TEST=Tested WFC camera on Brya
Change-Id: I1174606cd22cd353f01d865d0c25bb6f8f8de055
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.
For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.
For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.
For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.
Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Restructuring opregion VBT related code to make it more generalize
for future revision of opregion spec.
Moved logic to locate VBT from different region (CBMEM, PCI option
ROM or VBIOS) into separate function.
Created a new function to check if extended VBT region is required.
This will be helpful in the subsequent changes to determine if
extended VBT region is needed and handle memory allocation
accordingly.
BUG=None
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.
Change-Id: I479d57cd326567192a3cd1969f8125ffe1934399
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The loads of the FSPM and FSPS binaries are not insignificant amounts of
time, and without these timestamps, it's not clear what's going on in
those time blocks. For FSPM, the timestamps can run together to make it
look like that time is still part of the romstage init time.
Example:
6:end of verified boot 387,390 (5,402)
13:starting to load romstage 401,931 (14,541)
14:finished loading romstage 420,560 (18,629)
970:loading FSP-M 450,698 (30,138)
15:starting LZMA decompress (ignore for x86) 464,173 (13,475)
16:finished LZMA decompress (ignore for x86) 517,860 (53,687)
...
9:finished loading ramstage 737,191 (18,377)
10:start of ramstage 757,584 (20,393)
30:device enumeration 790,382 (32,798)
971:loading FSP-S 840,186 (49,804)
15:starting LZMA decompress (ignore for x86) 853,834 (13,648)
16:finished LZMA decompress (ignore for x86) 888,830 (34,996)
BUG=b:188981986
TEST=Build & Boot guybrush, look at timestamps.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This driver was inspired from soc/intel/common/block/pci/rtd3. I decided
to copy and modify it because the Intel driver has a lot of Intel
specific code.
This driver has been stripped down to only provide a power resource and
set the StorageD3Enable property. This driver is SoC agnostic and does
not handle suspending the actual PCIe root port. That should be
implemented by an SoC specific driver.
This is required for Guybrush to suspend/resume properly because the
NVMe power is tied to the S0 power rails, so the kernel needs to place
the device into D3.
BUG=b:184617186
TEST=Guybrush is able to suspend/resume properly. Also see power
resource get enabled / disabled.
[ 56.075559] power-0416 __acpi_power_off : Power resource [RTD3] turned off
[ 56.075562] device_pm-0279 device_set_power : Device [PXSX] transitioned to D3cold
[ 56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold
[ 56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs
[ 123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4
[ 123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0
[ 123.464982] power-0360 __acpi_power_on : Power resource [RTD3] turned on
[ 123.464984] device_pm-0279 device_set_power : Device [PXSX] transitioned to D0
[ 123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since the OS provides its own driver for the I2C controller it can
choose to use a bus speed other than the one used at coreboot runtime.
In this case it would be good to provide a way how the needed bus
timings are communicated to the OS, since these are very board-specific
and there is no way that the OS can know them other than read the
appropriate ACPI reported timings.
This patch adds some code to report additional bus speed timings if
there are some defined in the devicetree.
Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
As per the comments in CB:54090 mainboard api
mainboard_tcss_get_port_info() is simplified and moved to tcss common
block code.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This will be used to pass information to driver through ACPI in devicetree.
Example https://review.coreboot.org/c/coreboot/+/52013
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
TEST=Add these macros in devicetree, build and check static.c for consistency
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.corp-partner.google.com>
Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55097
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are cases where the RTC_VRT bit in register D stays set after a
power failure while the real date and time registers can contain rubbish
values (can happen when RTC is not buffered). If we do not detect this
invalid date and/or time here and keep it, Linux will use these bad
values for the initial timekeeper init. This in turn can lead to dates
before 1970 in user land which can break a lot assumptions.
To fix this, check date and time sanity when the RTC is initialized and
reset the values if needed.
Change-Id: I5bc600c78bab50c70372600347f63156df127012
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54914
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In commit b64db833d6 a basic ACPI support was added to the driver.
With this support an SSDT-entry is created for this RTC and it is now
visible to the OS via ACPI. In Linux the PNP-devices, which are
reported over ACPI, are scanned rather early and if the entry is found,
the device is claimed even if there is no driver available yet.
In this case, when the native RTC-driver without ACPI-support is loaded
and tries to register this device, the RTC is already blocked by the
PNP-drivers and cannot be used anymore. This leads to a non-usable RTC
on kernels where the needed ACPI-extension is not yet merged into the
RTC driver.
This patch provides a way to disable the ACPI-support for the RTC if
needed.
Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55003
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fsp_temp_ram_exit() function is only getting called by
late_car_teardown() function inside temp_ram_exit.c file.
Hence, make function as static and removed from include/fsp/api.h.
Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The only FSP 1.1 platform is Braswell. Drop unnecessary functions which
only have a weak stub definition.
Change-Id: Ie60213e5a6ae67bd8b982ee505f4b512253577c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The only FSP 1.1 platform is Braswell, which has a non-weak definition
for the `soc_silicon_init_params` function. This changes the resulting
BUILD_TIMELESS=1 coreboot image for Facebook fbg1701, for some reason.
Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The only FSP 1.1 platform is Braswell. Drop unused weak definitions for
functions where a non-weak definition always exists.
Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.
Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Commit 736a1028fb (drivers/intel/fsp1_1:
Drop dead MMA code) dropped FSP 1.1 MMA code, but missed a few things.
Change-Id: I556e7125eff21c49609bb1e5e1f23e99e692756f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
No board uses AMD PI 00630F01, so drop it. And drop a single reference
to the now-removed `NORTHBRIDGE_AMD_PI_00630F01` Kconfig option inside
the `drivers/amd/agesa/acpi_tables.c` file.
Change-Id: Ibc45a4a6041220ed22273c1d41f9b796e1acb901
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54897
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prepare to allow using other backends to store options.
Change-Id: I3f838d27bf476207c6dc8f2c1f15c3fa9ae47d87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Added SW_MUTE_DEVICE event type for mic mute switch.
BUG=b:184593945
BRANCH=puff
TEST=build image and verify with evtest on puff:
/dev/input/event3: mic_mute_switch
UI event_device_info receives the proper name.
Change-Id: I09c52dc3df63e266c73741b102a22f8a2b896791
Signed-off-by: Ben Zhang <benzh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Added the label field to the gpio_keys _DSD so that the kernel driver
can use a meaningful name instead of the generic _HID PRP0001.
BUG=b:184593945
BRANCH=puff
TEST=build image and verify with evtest on puff:
/dev/input/event3: mic_mute_switch
UI event_device_info receives the proper name.
Change-Id: I0377851b9cf23bab31930aed6e7de91b4ac3505b
Signed-off-by: Ben Zhang <benzh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Along with upstream kernel for Retimer firmware upgrade, coreboot
provides DFPx under host router where each DFP has its PLD and DSM. The
DFPx's functions encapsulates power control through GPIO, PD
suspend/resume and modes setting for Retimer firmware update under NDA
scenario.
BUG=b:186521258
TEST=Booted to kernel and validated host router's DFPx properties after
decomposing SSDT table.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I81bef80729f6df57119f5523358620cb015e5406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52712
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HSBIAS_SENSE_EN configures HSBIAS output current sense through
the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce
the potential pop noise during the headset plug out slowly. But on some
platforms ESD voltage will affect it causing test to fail, especially
with CTIA headset type. For different hardware setups, a designer might
want to tweak default behavior.
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Make the FSP notify phases name prior in comments section.
2. Fix discrepancies in FSP notify before and after postcode comments.
3. Add FSP notify postcode macros for after pci enumeration(0xa2)
and ready to boot(0xa3) call.
Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52894
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add backlight support in sn65dsi86bridge through the AUX channel using
eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board.
Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SN65DSI86 eDP bridge supports two ways to read the EDID: for now
we've been using "direct mode", which works by basically making the
bridge I2C device listen to another chip address besides its own and
proxy all requests received there directly to the eDP AUX channel. The
great part about that mode is that it is super easy and hassle-free to
use. The not so great part about it is that it doesn't work: for EDID
extensions, the last byte (which happens to contain the checksum) is
somehow always read as zero. We presume this is a hardware bug in the
bridge part.
The other, much more annoying way is "indirect mode", where each byte
transmitted over the AUX channel has to be manually set up in the I2C
registers of the bridge, just like we're already doing with DPCD
transactions. Thankfully, we can reuse most of the DPCD code for this so
it's not a lot of extra code. It's a bit slower but not as much as you'd
expect (26ms instead of 18ms on my board), and the difference is not
very relevant compared to common total times for display init.
Also, some of the (previously unused) enum definitions for the AUX_CMD
mode field of the bridge had just been plain wrong for some reason, and
needed to be fixed to make this work.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52959
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the options accessed within coreboot is a string, and there are
no guarantees that the code works as intended with them. Given that the
current option API only supports integers for now, do not try to access
options whose type is 's' (string).
Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
When using a hardware assisted root of trust measurement, like Intel
TXT/CBnT, the TPM init needs to happen inside the bootblock to form a
proper chain of trust.
Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51923
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The only use case for FSP-T in coreboot is for 'Intel Bootguard'
support at the moment. Bootguard can do verification FSP-T but there
is no verification on whether the FSP found by walkcbfs_asm is the one
actually verified as an IBB by Bootguard. A fixed pointer needs to be
used.
TESTED on OCP/Deltalake, still boots.
Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order for short circuit protection and over current protection to work, the
debug mode needs to be turned off.
BUG=b:185749961
TEST=build and test
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: Iacfa3c668a52d1bae15fe82f1c614d0ebd93a957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
If device is supported as a wake source, _S0W should be set to D3hot.
This ensures that the device is put into D3hot by the OSPM.
Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM.
The devices we are currently looking at for touchscreen/touchpad
do not really support auxiliary power and so do not support wake from D3cold.
BUG=b:186070097
TEST=build and check device wake state _S0W set to 3 in ssdt table.
Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR
available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and
therefore verstage is not possible either.
Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the recent switch to SMM module loader v2, the size of the SMM for
module google/volteer increased to above 64K in size, and thus failed to
install the permanent SMM handler. Turns out, the devicetree is all
pulled into the SMM build because of elog, which calls
`pci_dev_is_wake_source`, and is the only user of `struct device` in
SMM. Changing this function to take a pci_devfn_t instead allows the
linker to remove almost the entire devicetree from SMM (only usage left
is when disabling HECI via SMM).
BUG=b:186661594
TEST=Verify loaded program size of `smm.elf` for google/volteer is
almost ~50% smaller.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Inspired by discussion in CB:22822.
If I2C bus step response has not been measured, assume the layout to
have been designed with a minimal capacitance and SCL rise and fall
times of 0 ns. The calculations will add the required amount of
reference clocks for the host to drive SCL high or low, such that the
maximum bus frequency specification is met.
Change-Id: Icbafae22c83ffbc16c179fb5412fb4fd6b70813a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52723
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The procedure is identical for reads and writes. Factor it out.
Change-Id: I22b1d334270881734b34312f1fee01aa110a6db4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52636
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel
This was tested on the octopus/variants/fleex ainboard to ensure
that the SSDT contained the equivalent parameters that are provided
by the current DSDT object
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Change-Id: I7c3145b20a1ba743d91eb64b93cb001db3854c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With this change, the type-unsafe {get,set}_option() API functions are
no longer used directly. The old API gets dropped in a follow-up.
Change-Id: Id3f3e172c850d50a7d2f348b1c3736969c73837d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52512
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We had the addrspace_32bit rdev in prog_loaders.c for a while to help
represent memory ranges as an rdev, and we've found it useful for a
couple of things that have nothing to do with program loading. This
patch moves the concept straight into commonlib/region.c so it is no
longer anchored in such a weird place, and easier to use in unit tests.
Also expand the concept to the whole address space (there's no real need
to restrict it to 32 bits in 64-bit environments) and introduce an
rdev_chain_mem() helper function to make it a bit easier to use. Replace
some direct uses of struct mem_region_device with this new API where it
seems to make sense.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new configuration low_power_probe to avoid camera privacy LED
blink during the boot.
Change-Id: I27d5c66fb380ae6cd76d04ee82b7736407dac1b0
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52189
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The selector component in Sound Open Firmware (SOF) can consume all the
mics and use the configuration in the Use Case Manager (UCM) to select
the right channel. Hence dmic select gpio configuration is optional.
BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the machine driver
ACPI object is populated without DMIC select GPIO.
Change-Id: Iba00b07c3656c487e33bab184fefee7037745e2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52393
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IPMI debug was extra spewy, so add a debug option as SPI and
other drivers have when they need to be debugged.
Change-Id: I788d67c242cac23bde9750aa3e95e3276c3f1fd7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Traditionally, for each Intel platform using FSP, FSP-S has at some
point configured GPIOs differently than the mainboard configuration in
coreboot. This has resulted in various side-effects in coreboot,
payload and OS because of misconfigured GPIOs. On more recent Intel
platforms, a UPD `GpioOverride` is added that coreboot can use to
ensure that FSP does not touch any GPIO configuration.
This change adds a debug option `CHECK_GPIO_CONFIG_CHANGES` to fsp2_0
driver in coreboot that makes a platform callback `gpio_snapshot` to
snapshot GPIO configuration before making a call to FSP SiliconInit
and Notify phases. This snapshot is then compared against the GPIO
configuration using platform callback `gpio_verify_snapshot` after
returning from FSP. The callbacks are not added to romstage (FSP-M)
because mainboard configures all pads in ramstage.
This debug hook allows developers to dump information about any pads
that have a different configuration after call to FSP in ramstage. It
is useful to identify missed UPD configurations or bugs in FSP that
might not honor the UPDs set by coreboot.
This debug hook expects the platform to implement the callbacks
`gpio_snapshot` and `gpio_verify_snapshot`. These can be implemented
as part of the common GPIO driver for platforms using
FSP2.0+. Platforms that implement this support must select the config
`HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT` to make the debug config
`CHECK_GPIO_CONFIG_CHANGES` visible to user.
Proposal for the GPIO snapshot/verify support was discussed in the RFC
CB:50829.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I5326fc98b6eba0f8ba946842253b288c0d42c523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50989
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a driver for the TI TAS5825M smart amplifier [1].
The driver expects the mainboard using it to define tas5825m_setup(),
which uses the tas5825m_* functions to set configuration data. Each
mainboard may have very different configuration data, depending on
its audio hardware.
Tested on System76 addw1, bonw14, oryp5, and oryp6.
[1]: https://www.ti.com/product/TAS5825M
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the Intel MMA driver to use the new CBFS API.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ports the last remaining use of cbfs_boot_locate() in the
Intel FSP drivers to the new CBFS API. As a consequence, there is no
longer a reason for fsp_validate_component() to operate on rdevs, and
the function is simplified to take a direct void pointer and size to a
memory-mapping of the FSP blob instead.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f0239eefa4542e4d23f6e2e3ff19106f2e3c0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52281
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.
Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Rename the Kconfig parameter to more accurately reflect what it does.
TPM can be initialised in a different stage too, for instance with
VBOOT it is done in verstage.
Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This guards code accessing the vboot context which does not exist if
vboot starts after romstage.
Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Add definitions to describe GPIOs in generated ACPI objects.
The method allow either write a GpioInt() or Interrupt() descriptor.
Signed-off-by: Seven Lee <wtli@nuvoton.com>
Change-Id: I37fec7b0b9324dbfb61b7a8bea80f45026c54409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51922
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TPM_INIT depends on VBOOT but should also depend on
VENDORCODE_ELTAN_xBOOT.
Add dependency. TPM_INIT will be enable for measured boot only.
BUG = NA
TEST = Boot Facebook FB1701 with possible combinaties of VBOOT, measured
boot and eltan security.
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
The only FSP 1.1 platform with MMA support is Skylake. As it now uses
Kaby Lake FSP 2.0, this code is no longer useful. Drop it.
Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The Intel FSP 2.0 driver contains a custom construct that basically
serves the same purpose as the new CBFS allocator concept: a callback
function to customize placement of a loaded CBFS file whose size is
initially unknown. This patch removes the existing implementation and
replaces it with a CBFS allocator.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In pursuit of the eventual goal of removing cbfs_boot_locate() (and
direct rdev access) from CBFS APIs, this patch replaces all remaining
"simple" uses of the function call that can easily be replaced by the
newer APIs (like cbfs_load() or cbfs_map()). Some cases of
cbfs_boot_locate() remain that will be more complicated to solve.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since prog_locate() was eliminated, prog_rdev() only ever represents the
loaded program in memory now. Using the rdev API for this is unnecessary
if we know that the "device" is always just memory. This patch changes
it to be represented by a simple pointer and size. Since some code still
really wants this to be an rdev, introduce a prog_chain_rdev() helper to
translate back to that if necessary.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
IPMI OEM command set processor information has already been implemented
in u-root payload:
efdc3a30ec
Also this command has a higher chance to see BMC KCS timeout issue when
coreboot log level is 4, which can be avoided if this command is run at
a later stage such as LinuxBoot.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: If0081e5195cbd605e062723c197ac74343f79a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51276
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that SAR support in VPD is deprecated in coreboot, there is no
need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only
supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS`
from drivers/wifi/generic/Kconfig and its selection in
mb/google/.../Kconfig.
wifi_sar_defaults.hex is added to CBFS only if
CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards
do not provide a default SAR file in
coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a
default value of "".
BUG=b:173465272
Cq-Depend: chromium:2757781
Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch rewrites the last few users of prog_locate() to access CBFS
APIs directly and removes the call. This eliminates the double-meaning
of prog_rdev() (referring to both the boot medium where the program is
stored before loading, and the memory area where it is loaded after) and
makes sure that programs are always located and loaded in a single
operation. This makes CBFS verification easier to implement and secure
because it avoids leaking a raw rdev of unverified data outside the CBFS
core code.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7a5525f66e1d5f3a632e8f6f0ed9e116e3cebfcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
From ALSA reviewer suggest to change the name to RTL1015.
Details in below threads:
https://www.spinics.net/lists/alsa-devel/msg123395.html
BUG=b:177971830
TEST=: ALC1015P driver can probe properly.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2762852bdc3164346e3618c373aa4d3336415653
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Missing acpi_dp_write and correct the name from sdb to sdb-gpios for
driver.
BUG=b:177971830
TEST: ALC1015P driver can get sdb-gpio properly.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2728a7dad695d5c97e85c5d86b1effea1595da65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51379
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread
which indicates whether the work should be scheduled in a serially on all APs
or in parallel. Current implementation of this function mp_startup_all_aps
always schedules work in parallel on all APs. This implementation ensures
mp_startup_all_aps honors to run serialized request.
BUG=b:169114674
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.
Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml
BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find /sys/firmware/acpi/tables/ -type f) ; do
f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
{
Package (0x02)
{
"semtech,cs0-ground",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
Package (0x02)
{
"semtech,proxraw-strength",
Zero
},
Package (0x02)
{
"semtech,avg-pos-strength",
0x0200
},
Package (0x02)
{
"semtech,combined-sensors",
Package (0x03)
{
Zero,
One,
0x02
}
},
Package (0x02)
{
"semtech,resolution",
"finest"
}
}
Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch pulls control of the memory pool serving allocations from the
CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the
CBFS API. Previously, platforms would independently instantiate this as
part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache
pool is exported as a global so these platforms can still use it to
directly back rdev_mmap() on their boot device, but the cbfs_cache can
now also use it to directly make allocations itself. This is used to
allow transparent decompression support in cbfs_map().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use lowercase `port` in both the spec and the body.
Change-Id: I3d1e2abe03eedcaf57716af444a3e3b8a61b60d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily)
the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was
removed. In the meantime Seiko-Epson did a great job and registered an
official vendor ID in the ACPI database [1]. Further on, Seiko-Epson
has now assigned the unique Product Identifier for the RX6110SA, which
is '6110'. The assignment of the Product Identifier is controlled by
the vendor and there is no official database where this ID is stored
in. It is up to the vendor to make sure that this ID stays unique.
This patch adds this new vendor and product ID to the driver. Together
with a pending Linux patch this RTC is now useable as ACPI device in
Linux.
[1] https://uefi.org/ACPI_ID_List?search=SECC
Change-Id: I45838162f014a760520692c6dcaae329ad98547d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51176
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RAM is not yet configured in bootblock. This function was copy-pasted
from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in
there can be removed as nothing else uses them.
Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds new soundwire device ALC1308
The codec properties are filled out as best as possible
with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
The unique ID is calculated from schematics by referring to ASEL[1:0]
strap settings. Datasheet of ALC1308 provides info about the mapping of
ASEL strap settings to unique ID
For example this device is connected to master link ID 1 and has strap
settings configuring it for unique ID 2.
chip drivers/soundwire/alc1308
register "desc" = ""Left Speaker""
device generic 1.2 on end
end
Bug=None
Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for
PCI0.HDAS.SNDW are present for ALC1308
Test speaker out functionality
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From JSL FSP v2376 "FirmwareVersionInfo.h" header file is
added and "FirmwareVersionInfoHob.h" is deprecated. This patch
adds support to display firmware version information using
"FirmwareVersionInfo.h" header file.
Changes included in this patch:
- Add Kconfig to select FirmwareVersionInfo.h
- Add code change to display firmware version info using
FirmwareVersionInfo.h header
No change in version info print format.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
FSP expects mp_get_processor_info to give processor specfic apic ID,
core(zero-indexed), package(zero-indexed) and thread(zero-indexed) info.
This function is run from BSP for all logical processor, With current
implementation the location information returned is incorrect per logical
processor. Also the processor id returned does not correspond to the
processor index, rather is returned only for the BSP.
BUG=b:179113790
Change-Id: Ief8677e4830a765af61a0df9621ecaa372730fca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50880
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the UPD size in coreboot sizes mismatches the one from the FSP-M
binary, we're running into trouble. If the expected size is smaller than
the UPD size the FSP provides, call die(), since the target buffer isn't
large enough so only the beginning of the UPD defaults from the FSP will
get copied into the buffer. We ran into the issue in soc/amd/cezanne,
where the UPD struct in coreboot was smaller than the one in the FSP, so
the defaults didn't get completely copied.
TEST=Mandolin still boots.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related
bits in "Link Capability Register" and "L1 PM Substates Capabilities
Register". coreboot overrides these configs even if the driver sets
them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is
redundant and useless.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" prints are identical with and without this patch;
LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch.
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot sets up certain configs (e.g. L1ss) based on the device's
reported capacities; however, this BayHub lv2 driver modifies some
of its capacities after coreboot uses them. Therefore, coreboot may
make incorrect configs based on out-of-date capacities.
This patch moves the driver from ".init" to ".enable" so that the
capacities are set before the rest of coreboot queries them.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1
of both PCI device "00:01.3" and "02.00.0"
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
This change ensures that the IRQ is appropriately configured.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild. Build and boot to OS in Dedede.
Change-Id: I3245a9de6e88cd83528823251083e62288192f0d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Enforcing the exact match of FSPS UPD block size between FSP and
coreboot mandates simultaneous updates to coreboot and FSP repos. Allow
coreboot to proceed if its UPD structure is smaller than FSP one. This
usually indicates that FSPS has an updated (larger) UPD structure which
should be soon matched/updated on the coreboot side to keep them in
sync.
While this is an undesirable situation that should be corrected
ASAP, it is safe from coreboot perspective. It is safe (as long as
default values in FSP UPD are sane enough to boot) because FSPS UPD
buffer is allocated on the heap with the size specified in FSPS
(larger) and filled with FSPS default values. This allows FSP UPD
changes to be submitted first followed by changes in coreboot repo.
Note that this only applies to the case when entire FSPS UPD structure
grows which should be rare as FSP should allocate enough reserve space,
anticipating future expansion, to keep the structure from growing when
new members are added.
BUG=b:171234996
BRANCH=Zork
TEST=build Trembyle
Change-Id: I557fd3a1f208b5b444ccf76e1552e74ecf4decad
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Only the call in `spi_flash_cmd_write_page_program` uses non-constant
values for the array length. However, the value for `data_len` has an
upper bound: `flash->page_size` is set to `1U << vi->page_size_shift`
which depends on the flash chip vendor info, and the largest value it
can currently have is 8. Thus, the maximum page size is currently 256.
Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on
the amount of data that can be written in one command. Then, use this
value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also,
add a check to prevent buffer overflow problems. Finally, ensure that
the `spi_flash_cmd_write_page_program` function always writes no more
than 256 bytes of data when using the `spi_flash_cmd_write` function.
Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works.
Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Hide the detail of allocation from cbmem from the FSP.
Loading of a BMP logo file from CBFS is not tied to FSP
version and we do not need two copies of the code, move
it under lib/.
Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.
This implementation also selects the respective MP services PPI version
supported for SoCs
BUG=b:169196864
Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.
FSP_PEIM_TO_PEIM_INTERFACE is used for:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
* Adding ppi to subdirs-y
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
and is selected by SoCs that want to enable MP PPI services.
Instead of using the indirect path of selecting MP PPI services, this
change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The
above uses are handled as follows:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
--> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI.
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
--> The guard isn't really required. The Kconfig options in this
file don't present user prompts and don't really need to be guarded.
* Adding ppi to subdirs-y
--> Makefile under ppi/ already has conditional inclusion of files
and does not require a top-level conditional.
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
--> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.
TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom
Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a driver which puts the device into power-saving mode.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Use probe_resource instead of find_resource. This prevents
a call to die and instead returns NULL.
* Handle the case where BAR2 isn't present
* Don't hardcode legacy VGA when BAR2 is present. This fixes
graphic initialisation when the Aspeed isn't the primary GPU
and thus doesn't decode VGA cycles.
This makes the coreboot code more similar to the Linux kernel code.
Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BH720 PCR registers are accessed using an index/data register pair.
Introduce some helper functions to clarify the PCR register operations.
Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard
into drivers/ipmi/ocp to avoid code duplication and provide better
reusability.
2. OCP Tioga Pass enables IPMI_OCP driver.
Tested=On OCP Delta Lake and Tioga Pass verify the commands still work
correctly.
Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.
There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
causes problems with cbfs_mcache)
Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In case of a mismatch print both the UPD signature in the FSP and the
expected signature and then calls die(), since it shouldn't try calling
into the wrong FSP binary for the platform.
Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Factor out the condition when an attempt to load
stage from cache can be tried.
Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The function has only one local call-site.
Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Except for one debug print in sarien, both functions are identical.
Move them to driver code to avoid unnecessary redundancy.
Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
It was confusing to have this defined while there was another
symbol bootblock_protected_mode_entry that was not really used
as an entry point.
Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to FSP_INFO_HEADER structure in FSP EAS v2.0-v2.2,
BIT1 indicates an "official" build.
Change-Id: I94df6050a1ad756bbeff60cda0ebac76ae5f8249
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There's no need to repeat the same code on every board.
Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the "ERROR:" tag so that it ease debug effect.
TEST=Test tools like "suspend_stress_test" (specific to Chrome OS) can
identify the obvious coreboot ERROR prior running S3 resume test.
Change-Id: I64717ce0412d43697f42ea2122b932037d28dd48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49798
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
