Commit graph

1329 commits

Author SHA1 Message Date
Patrick Georgi
0c00f9a58f arm: Include types.h in clock.h
... so uint32_t is known by the time it's used.

Change-Id: I7281e869ce2e00165a0e21bc017aa6c0e27827b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9333
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-07 18:47:39 +02:00
Furquan Shaikh
6f33f0a87d arm64: Add verstage support
This stage is not tested on any hardware.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush_ryu and veyron_pinky

Original-Change-Id: I6dd266471c815895bb3dd53d34aacc8fe825eeb6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221911
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

(cherry picked from commit 907ea2d1f8c9f01d815e8673695dd5271322c7a8)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I617a742d4a387be947086dae33e9a913f742a8d1
Reviewed-on: http://review.coreboot.org/9255
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07 18:06:28 +02:00
Stefan Reinauer
a48ca841a2 kconfig: drop intermittend forwarder files
With kconfig understanding wildcards, we don't need
Kconfig files that just include other Kconfig files
anymore.

Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9298
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-07 17:40:28 +02:00
Julius Werner
ec5e5e0db2 New mechanism to define SRAM/memory map with automatic bounds checking
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06 22:05:01 +02:00
Patrick Georgi
828e0e86f3 build system: run linker scripts through the preprocessor
This allows combining and simplifying linker scripts.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Ie5c11bd8495a399561cefde2f3e8dd300f4feb98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9303
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-06 19:14:00 +02:00
Paul Menzel
9484f5577e arch/arm64/boot.c: Only return if condition is met
Fix up commit b3847e64 (program loading: add prog_run() function),
which misses the braces for the if statement, causing the function
also to return if a non-payload program should be run causing the rest
of the stages never to be run.

Change-Id: I04940b218ba71e82af769c8db574528f830d0cbb
Found-by: Coverity, CID 1293136: Control flow issues (NESTING_INDENT_MISMATCH)
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/9306
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-06 02:21:26 +02:00
Alexander Couzens
e19c8b0091 acpi: protect acpi generators from PRE_RAM & SMM
acpi generators run only in RAM stage.

Change-Id: Ia2ab677848fef38976c85dda1c2773ae065856b0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9249
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-04-05 04:07:25 +02:00
Patrick Georgi
56b830938a build system: rename __BOOT_BLOCK__ and __VER_STAGE__
Drop the inner underscore for consistency. Follows the
commit stated below.

Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06
Based-on-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172
Reviewed-on: http://review.coreboot.org/9290
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-04-04 20:07:18 +02:00
Patrick Georgi
990e7c90f0 build system x86: deprecate bootblock_lds and ldscripts variables
Instead of keeping this separate variable around, add linker scripts
to the $(class)-y source lists and let the build system sort things out.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I4af687becf2971e009cb077debc902d2f0722cfb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9289
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04 20:07:12 +02:00
Patrick Georgi
d69839bdfd build system: use full (in-tree) paths
So far we assumed that all files in *-srcs are below src/
which wasn't really true actually and will be less true with
future changes.

Fix up crt0.S handling on x86, which is covered by default rules
due to this change.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Icae563c2d545b1aea809406e73faf3b417796a1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9288
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04 20:06:55 +02:00
Aaron Durbin
8adf1bf2f3 arm64: make secmon link with the manual template
Secmon needs a special build rule because of the objcopy -B
operation required to include it in ramstage. Utilize the
manual template so builds continue to work with upcoming
build chnages.

Note: secmon is actually missing symbols still so those
still need to be addressed. That looks to be as if
--gc-sections isn't be honored, but I'm actually thinking
the symbols are just erroneously carried over as the
references for these symbols don't show up in the
symbol table:
 U coreboot_build
 U coreboot_extra_version
 U coreboot_version
 U default_baudrate
 U lb_add_console
 U lb_add_serial
 U uart_baudrate_divisor

Change-Id: I41c75e93536b73c4304ef3a87dc39d448d1f00d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9300
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04 09:05:27 +02:00
Furquan Shaikh
1ea2e76035 armv4: Add verstage to armv4
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I7735a2148da5330f220bd9a87b09e9fe3e37ffd1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221322
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

(cherry picked from commit 5e43dfe1aab813f45f1123b0e2432cdab5738d87)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: If3d89ab79bae6d8f1b6f2d89b7693a79dca02476
Reviewed-on: http://review.coreboot.org/9252
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-04 04:04:24 +02:00
Furquan Shaikh
dfb8eb104a armv7: Add config option guard for verstage class
Add files to verstage class depending upon value of
CONFIG_ARCH_VERSTAGE_ARM_V7.

BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I60fb8390abd9d378e38511d4f4ac323b43450232
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221321
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

(cherry picked from commit 4889cb73b0579155c083bb5fa2895b4d52ab0a56)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iea788ed72344343b2e7a3d91cd7f27ce20f4f177
Reviewed-on: http://review.coreboot.org/9251
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-04 04:04:15 +02:00
Patrick Georgi
f1df82a458 x86: rename ldscript_failover.ld to failover.ld
The ldscript_ prefix is redundant.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I0f005c0c2abe2fdd6911a2c579cb7ec49ae5c0b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9284
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04 00:41:35 +02:00
Aaron Durbin
ce9efe061a program loading: unify on struct prog
Instead of having different structures for loading
ramstage and payload align to using struct prog.
This also removes arch_payload_run() in favor of
the prog_run() interface.

Change-Id: I31483096094eacc713a7433811cd69cc5621c43e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8849
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03 14:53:11 +02:00
Aaron Durbin
b3847e6424 program loading: add prog_run() function
The prog_run() function abstracts away what is required
for running a given program. Within it, there are 2
calls: 1. platform_prog_run() and 2. arch_prog_run().
The platform_prog_run() allows for a chipset to intercept
a program that will be run. This allows for CPU switching
as currently needed in t124 and t132.

Change-Id: I22a5dd5bfb1018e7e46475e47ac993a0941e2a8c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8846
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03 14:52:47 +02:00
Aaron Durbin
3948e5392b program loading: introduce struct prog
The struct prog serves as way to consolidate program
loading. This abstraction can be used to perform more
complicated execution paths such as running a program
on a separate CPU after it has been loaded. Currently
t124 and t132 need to do that in the boot path. Follow
on patches will allow the platform to decide how to
execute a particular program.

Note: the vboot path is largely untouched because it's
already broken in the coreboot.org tree. After getting
all the necessary patches pushed then vboot will be
fixed.

Change-Id: Ic6e6fe28c5660fb41edee5fd8661eaf58222f883
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8839
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03 14:51:51 +02:00
Julius Werner
c3e7c4e7b4 Clean up architecture-specific Kconfigs
It's an unfortunate side effect of our different-archs-per-stage
mechanism that all src/arch/*/Kconfig files are always parsed with no
if blocks to exclude them if they're not relevant. This makes it very
easy to accidentally rely on a Kconfig default set by a totally
different and not applying architecture.

This patch moves a few Kconfigs from ARM and X86 that leaked out like
this into a common Kconfig file for clarity. It also gives ARM64 its
own BOOTBLOCK_CUSTOM mechanism so that it doesn't leech off the ARM one
(currently not used by any board).

In the future, we should maybe prefix all options in the arch/*/Kconfig
files with the architecture name (such as X86_BOOTBLOCK_NORMAL and
ARM_LPAE are already doing), to make it more apparent when they are used
in the wrong place.

BUG=None
TEST=None (tested together with dependent changes)

Change-Id: I3e8bb3dfbb2c4edada621ce16d130bd7387d4eb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5528aa9252cdf711af3c160da387c6a7bebe9e76
Original-Change-Id: Ieb2d79bae6c6800be0f93ca3489b658008b1dfae
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219171
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9235
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02 22:06:31 +02:00
Patrick Georgi
db273065f6 build system: extend src-to-obj for non-.c/.S files
It also creates file names in the build directory and with
the stage sliced in, but keeps the extension for anything
not .c or .S.

Also some handling for non-.c/.S files was adapted to match.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: If8f89a7daffcf51f430b64c3293d2a817ae5120f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9175
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-04-02 22:06:29 +02:00
Vadim Bendebury
b92e54333f mips: do not place branch instructions in branch delay slot
A branch instruction in a branch delay slot confuses the execution
pipeline and causes an exception.

bootblock.S was written 'by hand', has a branch instruction in branch
delay slot and includes '.set noreorder' directive, which causes it to
crash when trying to branch to main().

Adding a nop instruction fixes the problem. Also adding a nop after
the last branch in the file just in case main() returns and the object
linked next starts with a branch.

BUG=chrome-os-partner:31438
TEST=Running on the simulator can reach main() now

Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9183
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-04-02 21:43:16 +02:00
Julius Werner
635ee51b0d arm: Prevent compilation of old, experimental SMP support
The ARM SMP feature was added a long time ago and has never really been
used by anyone since. We are still always compiling cpu_info() even
though we don't use it, and it makes some dangerous assumptions about
stack alignment that are not guaranteed anywhere.

I'm planning to change the way the stack boundaries are defined. Rather
than trying to work that into this unsafe, unused and hard to test
feature, I think we should just seal it off with police tape and make
sure that if anyone ever tries to use it again (which currently seems
unlikely), they get forced to do their due diligence on making sure it
works as intended.

BUG=None
TEST=Compiled Veyron_Pinky.

Change-Id: Id25545cab88f29200c7672ef02c7804f0ac26399
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 5b517fc46b030a6e50ef2f5e4d4a449b98ce16c6
Original-Change-Id: I8a60bd30e8b27a22bb3da68ca84daea99424dee9
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219680
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9222
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02 17:27:54 +02:00
Kane Chen
51bdc47816 smbios: add a family id in smbios type1 family
mosys will use this field to identify system

BRANCH=none
BUG=chromium:359155
TEST=build ok, use dmidecode to check whether data is
     written correctly

Change-Id: I461215c012b6ad712b3f813a3928e90a23bf54f1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 7adbdab761cd7b4bda0a43e7b1c4070de26f150a
Original-Change-Id: Icfbd4c61fc49a9cb3d3ecd2b622339957963150c
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217400
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9230
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02 13:26:05 +02:00
Aaron Durbin
9eebbd4151 x86: set smbios rom size based on CONFIG_ROM_SIZE
Instead of relying on the CBFS header's romsize field use
the CONFIG_ROM_SIZE Kconfig variable. That value is what is
used to create the rom file as it is. Therefore, just remove
the dependency.

Change-Id: If855d7378df20080061e27e4988e96aee233d1e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9130
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-01 22:54:28 +02:00
Aaron Durbin
f786652af1 cbfs: add cbfs_serialized.h header file
The serialized format of CBFS is separate from the APIs
used to traverse and read from CBFS. Separate those out
so they can be consumed as a standalone header.

Change-Id: I09f71d9c474ee9f23a62b0062ffa777963d1a4dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9125
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31 23:01:39 +02:00
Aaron Durbin
7c2eb0d78b mips: don't open code romstage loading
Use the run_romstage() API to prevent code duplication
and more maintenance for any API changes or features.

Change-Id: I4122b813cccf4dc0703f256e1245deeeb90deeb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9172
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-31 07:55:25 +02:00
Patrick Georgi
3bc2999cb0 mips: bring payload execution to current standards
Change-Id: Id7f438a95fc7c7b41ce3d0fb419b0b455f8367a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9167
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:24 +02:00
Patrick Georgi
6f723c2692 mips: fix write_table
This replicates commit 3f7ad7b216 and
commit 823edda98e for mips.

Change-Id: Id97e1fefa20cfa3bcb2cf0336b5a4ff7d9fe813b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9166
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:23 +02:00
Patrick Georgi
146d05da93 imgtec/pistachio: Bring uart driver to modern standards
The console interface changed in upstream, and the
driver didn't reflect that yet.
This wasn't obvious because the driver wasn't compiled
at all.

Change-Id: Id18391e62e7ebd8f5fc929838ce27bf414e364f9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9165
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:22 +02:00
Patrick Georgi
6b65f0d8bd mips: Simplify architecture specific Makefile.inc
The mips Makefile was inherited from x86 and so included lots
of stuff that is necessary on x86 but nowhere else.
That cruft is now gone.

It also adopts the non-x86 approach of handling linker scripts,
hardcoding an include to ldoptions there, instead of manual
concatenation (of just one file plus options).

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Ibf0c7096f9425572d8f83837aa6a253fd91e212c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-30 20:41:20 +02:00
Patrick Georgi
2459aeea0b build system: provide generic compiler flag variables
Introduce generic-$(type)-ccopts and $(class)-generic-ccopts
to declare compiler flags that apply to all files of a certain
type or of a certain class. Then use them.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I655688e82a0cc5bad89b6f55dc217b9f66b64604
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:13 +02:00
Patrick Georgi
08f2ab6aac build system: rename mips/bootblock.inc to mips/bootblock.S
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I192fa50989b586fd8e967d4c22db56ac9de7a30e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9108
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:11 +02:00
Patrick Georgi
99f1a61a42 mips: add verstage configuration
Change-Id: I79b4969c34500fd51b1ce2ad751bc0723ee0afa2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9147
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 22:38:53 +02:00
Timothy Pearson
4785f2a358 arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make public
Change-Id: Ib85701965337bb6231d8df59d43789dfe8a036d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9136
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-29 16:34:07 +02:00
Timothy Pearson
821217b60f arch/x86/boot/smbios: Add additional SMBIOS defines and enums
Change-Id: I337584d1f4ce32094c24478a99418e0775cf9ab5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9135
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 16:33:00 +02:00
Patrick Georgi
68bfe16b44 armv8/secmon: SECMON_SRC is really SECMON_BIN
It points to a binary.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I164d7f717a9523d187e2c215083e176b59fd5acc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9113
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:15:57 +01:00
Patrick Georgi
70a6b4f931 arch/x86: Guard option table specific rules with HAVE_OPTION_TABLE
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Ia22c9fcbf8c629d0eb3f1356f80c4565f117d8b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9110
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:15:54 +01:00
Patrick Georgi
ea9f308018 build system: normalize linker script file names
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-28 19:14:47 +01:00
Patrick Georgi
276ff99a07 arch/arm64: Drop extra comment
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I362e2f6a978de23e72e6fc9c83bc99457cd76d9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:14:37 +01:00
Patrick Georgi
58fef67436 arch/arm: drop extra comment
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I8a5dc66d8c0dc4ccdb6dc3d66b8cdbf50dc976ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9111
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:14:34 +01:00
Aaron Durbin
910a00dc30 mips: fix API expectations that break builds
Add the approrpiate car* empty implementations as well as types
included within the rest of coreboot to start building correctly.

Change-Id: Ifaf10281f9a9e28f518f4694630cbffa3f8d187d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9150
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
2015-03-28 16:44:24 +01:00
Aaron Durbin
cd72103021 arm64: remove EL and mode from secmon_params
Since PSCI dynamically determines which EL to transition
to based on SCR_EL3 there's no need to provide that
information.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel with MP.

Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c
Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218924
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:44:54 +01:00
Aaron Durbin
bda3577d0c arm64: add psci support to secmon
The PSCI functionality initially includes CPU_ON and CPU_OFF
functions. Upon entering secmon if the parameters are non-NULL
then a PSCI CPU_ON action is done for the current CPU.

BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel
     using PSCI. Turned CPUs on and off.

Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748
Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9097
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-03-28 08:44:50 +01:00
Aaron Durbin
93eea8822d arm64: Provide secmon trampoline for restart
If an exception is taken that the secmon won't return
to, there needs to be way to reset that cpu's state
w.r.t. stack usage. Therefore, provide secmon_trampoline
which will reinitialize the exception stack and SP_EL0
and start executing with SP_EL0 like the initial state
of the secmon entry.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also tested when PSCI
     is employed in the kernel.

Change-Id: Ie9f5bbe715dcbcf8b67ea40f9a3a5088ac7aa2ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1f546ee3e9eca93baaa1ae0437351205bf548a5
Original-Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9096
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-03-28 08:44:48 +01:00
Aaron Durbin
40edd3864f arm64: fix smc bugs in secmon
Two things:
1. Not returning once setting the return state.
2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x))

With these 2 changes arguments and results are being processed
correctly.

BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and brought up SMP using PSCI.

Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8
Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9094
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:38 +01:00
Aaron Durbin
b241f57de5 arm64: add smc layer to secmon
In order to process PSCI commands SMC instructions need to be
serviced. Provide a simple way for users of SMC to register their
handlers by function.

The SMC layer hooks into the exception processing, however it only
processes AARCH64 SMC calls. All others are ignored.

BUG=chrome-os-partner:32112
BRANCH=None
TEST=Added nop smc call to depthcharge. SMC handled and continue booting
     to kernel.

Change-Id: I378f13c29220ff9f37040f094bf9cfb69259af0c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76d2febc50397348b68d38532b8f37e2b3cf6a30
Original-Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218846
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9092
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:37 +01:00
Aaron Durbin
e702be692b arm64: initialize secmon environment
The exception vectors were not reinitialized in secmon yet.
Add that as well as the split BSP vs non-BSP path. In doing
so bring in the cpu.c semantics for determining bsp at runtime.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also noted only one CPU
     printing messages.

Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32
Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218845
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9091
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:36 +01:00
Aaron Durbin
dee1996d6c arm64: provide entry points for BSP and non-BSP
It's helpful to differentiate the startup paths for
the BSP and the non-BSP. Therefore have c_entry
be an 2 element array of function pointers. The
non-BSP paths have an entry point one instruction after
stage/module entry.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel.

Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe
Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218844
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9090
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:35 +01:00
Aaron Durbin
b30c9b1c9a arm64: split cpu.c
The cpu.c contains some helpful construts as well as ramstage
devicetree handling. Split the 2 pieces so that cpu.c can be
reused in secmon.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted.

Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f
Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218842
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9089
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:34 +01:00
Aaron Durbin
4f89d97c06 arm64: exception handler registration
In order to build upon the arm64 exception handlers need
to be registered. This provides very basic support to
register a handler for a specific exception vector.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel.

Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a
Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218650
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9088
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:34 +01:00
Aaron Durbin
5add43574d arm64: add spin table support
There was a hacky and one-off spin table support in tegra132.
Make this support generic for all arm64 chips.

BUG=chrome-os-partner:32082
BRANCH=None
TEST=Ran with and without secure monitor booting smp into the kernel.

Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748
Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218654
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9084
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 07:05:13 +01:00