Our GDB doesn't support RISC-V yet, so let's disable it for now
to keep the build from breaking.
Change-Id: Iecc6d97fb16d16410c56965abeea55c67800f220
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
With this change you can say
$ make DEST=/opt/cross-1.35
to get all of the cross toolchain built and installed to /opt/cross-1.35
Change-Id: Icc3e605c4824bfa2831d030e4ed9dd0331ff722f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13847
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
qemu-power8 wants to tell about itself with XML, and so
we need to build gdb with EXPAT so it can understand XML.
Change-Id: I460e27f883956ed5d54e6070916e2682ee0f7a1b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13846
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Intel Speed Shift Technology is a new mechanism that replaces
Legacy P-state. ISST allows OS hints about energy/performance
preference. H/W performs the actual P-state control (autonomous)
1. Optimization frequency seclection for low residency workloads,
no longer a static knee point.
2. Optimized frequency selection for best energy to performance
trade offs.
3. Kick down frequency (from idle) fpr best responsiveness while
taking energy consumption init account.
Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
and enable HWP accordingly.
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu and verify HWP getting enabled/disabled
using Intel P-state driver.
Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313107
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://review.coreboot.org/13835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This dependency wasn't called out before, and when building with enough
threads, the build would fail due to a collision trying to build
build/util/kconfig/conf.
Fixes this failure:
make[1]: execvp: build/util/kconfig/conf: Permission denied
/home/martin/git/coreboot/util/kconfig/Makefile:40: recipe for target
'oldconfig' failed
make[1]: *** [oldconfig] Error 127
Makefile:167: recipe for target 'build/config.h' failed
Change-Id: Ib78d36bab0ba469796d89877bbe6a61e05196e87
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13859
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update the DPTF configuration for the chell mainboard:
1) Enable DPTF charger control, set max current to 1975mA
according to the battery specification.
2) Enable charger effect on charger temp sensor in TRT
3) Set PL2 to 15W which is the same value configured in the CPU.
BUG=chrome-os-partner:49859,chrome-os-partner:50306
BRANCH=glados
TEST=build and boot on chell
Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c
Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329187
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13842
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add new GPIOs for touchscreen enable and reset pins and define
the one missing unconnected pin for GPP_E10.
BUG=chrome-os-partner:50518
BRANCH=glados
TEST=build and boot on chell DVT1
Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d
Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329297
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13841
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is used in coreboot-side vboot code now, to keep booting from
the same RW section after wakeup - necessary when romstage is in RW
and its use of the RAM init configuration cache may differ between
versions.
Change-Id: Ie531cf3ddc980154f48772b3ff87e23473010721
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If a platform does verification of the memory init step, and it must
resume with the same slot that it booted from then it needs to set
the vboot context flag when resuming instead of booting. This will
affect the slot that is selected to verify and resume from.
BUG=chromium:577269
BRANCH=glados
TEST=manually tested on chell:
1) ensure that booting from slot A resumes from slot A.
2) ensure that booting from slot B resumes from slot B.
3) do RW update while booted from slot A (so the flags are set to try
slot B) and ensure that suspend/resume still functions properly using
current slot A.
4) do RW update while booted from slot B (so the flags are set to try
slot A) and ensure that suspend/resume still functions properly using
current slot B.
Change-Id: I77e6320e36b4d2cbc308cfb39f0d4999e3497be3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4c84af7eae7b2a52a28cc3ef8a80649301215a68
Original-Change-Id: I395e5abaccd6f578111f242d1e85e28dced469ea
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328775
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The FBC hardware for skylake does not have access to the bios_reserved
range so it always assumes 8MB is used and so the kernel will
therefore need to avoid using the last 8MB of the stolen window.
With the default stolen size of 32MB(-8MB) there is not enough space
for FBC to work with a high resolution panel.
Kernel reference:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a9da512b3ed73045253afd778e40d4298f42905b
BUG=chrome-os-partner:50396
BRANCH=glados
TEST=build and boot on chell DVT
Change-Id: I3049d7d9e7c551aad5b8fd1630d5fbd88ccb2692
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fff1f4b35e23e77cdc72c5bcc290f199494cdbbb
Original-Change-Id: If468cca5759a320f3cd2d7eb09f4bcc0117b24cb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328813
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of relying on power-on-reset values provide configuration
for all pads. PAD_CFG_NC() was used for all pads which had no nets
routed on the board. PAD_CFG_GPO(0) was used for pads which had nets
routed on the board in order to terminate them.
BUG=chrome-os-partner:50301
BRANCH=glados
TEST=Built and booted chell. Suspended and resumed on EVT.
Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9
Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327835
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13831
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable the EHCI and OHCI controllers.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when at the UEFI shell prompt:
* After issuing:
* "connect -r"
* "map -r"
* The "dir" command displays the contents of the USB flash drive
* A USB keyboard can issue shell commands
* The "drivers" command shows an EHCI and OHCI connection
Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Initialize the base addresses for:
* Power management control
* Power management status
* Reset
* Power management timer
* General-Purpose Event 0
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when:
* Register address are properly displayed by the payload
* "reset -c" performs a reset and reboots the system
* "reset -w" performs a reset and reboots the system
* "reset -s" performs a reset and turns off the power
Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13764
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add more documentation on the features that the EDK-II
CorebootPayloadPkg is using. Add 8254 and 8259 documentation
links. Add EDK-II documentation links.
TEST=Boot CorebootPayloadPkg to shell prompt
Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a link to the ACPI specification.
Update the FADT table to better describe the use and ACPI specification
reference for the various fields.
TEST=None
Change-Id: I77cd925800d71398be6d677de48874099ea26479
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Without this change it'll get a build error with crossgcc-x64
because $(AS) is "util/crossgcc/xgcc/bin/x86_64-elf-as --32",
and running $(LPAS) (i.e. AS=$(AS) lpas) will run "--32" instead of
"x86_64-elf-as".
Change-Id: I95e5630cb1d4f1ce81a8ca8a7bf338450b325f02
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13845
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
I first found the missing of #include guards when I tried to include
both sandybridge/gma.h and sandybridge/sandybridge.h, but
sandybridge.h includes gma.h in it and gives a compile error.
Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This allows coreinfo to be added to CBFS as a 'secondary'
payload on x86 systems, to be loaded by the main payload
if desired.
Selecting this option, which defaults to no, builds the coreinfo
payload and adds it to CBFS as `img/coreinfo` which can then be
loaded by for example SeaBIOS or GRUB.
Change-Id: I52661d486823bc4bb215ce92dca118c9d2c2a309
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13728
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Users had to build nvramcui manually because payload.sh was only meant
for abuild. Now the user can build it with:
cd payloads/libpayload/ && make menuconfig && make && make install
cd ../nvramcui && make
Change-Id: I409a3c39a1e1738e8071febb1a3f169e1aee959a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/13778
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
bit (bit 10) was checked in the "SDRAM Bus Width Status" register
to determine DRAM width.
Query bit 6 instead in accordance with the Aspeed AST2050 datasheet
v1.05.
Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13807
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Improved version of
I1a115a45d5febf351d89721ece79eaf43f7ee8a0
The first version wasn't well tested due to the lack of hardware
and it was to aggressive.
With timC being direct function of timB's 6 LSBs it's critical to match
timC and timB.
Some tests increments the value of timB by a small value,
which might cause the 6bit value to overflow, if it's close
to 0x3F.
Increment the value by a small offset if it's likely
to overflow, to make sure it won't overflow while running
tests and bricks the system due to a non matching timC.
In comparission to the first attempt, only 4 out of 128 timB values
are considered bad.
Needs test on real hardware !
Fixes a "edge write discovery failed" on my test system.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It was tested with a mini-PCI POST card on a Toshiba
Satellite 1410 laptop with the stock BIOS.
Change-Id: Icdc0860e2c72b17862601c2cc59eaf0f3d8a0e54
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/13763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that the SoC is configuring the UART pads there's no need to
implement bootblock_mainboard_early_init(). Remove it and
bootblock.c.
Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13794
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Provide a bootblock_soc_early_init() to that takes care of
initializing the UART on behalf of the mainboard when serial
console is enabled.
Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13793
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Instead of pushing the same code into each mainboard for configuring the
the UART pads and initializing the host contoller provide a function
to perform all the actions on behalf of the mainboard. The set of pads
configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option.
Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13792
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
There was no 'early' call into the SoC code prior to console
getting initialized. Not having this enforces the mainboard to
drive the setup of the console which typically just ends up
calling into the SoC code. Provide a SoC early init call
to handle this without having to duplicate the same code
in mainboards utilizing the same SoC.
Change-Id: Ia233dc3ae89a77df284d6d5cf5b2b051ad3be089
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13791
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
GPIO_187 is the beginning of the Northwest community pads.
Change-Id: I5565ecf534530144e80c65d886db11b53f38f935
Signed-off-by Aaron Durbin <adurbin@chormium.org>
Reviewed-on: https://review.coreboot.org/13789
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SOC_UART_DEBUG which does all the appropriate selection of the
dependent Kconfig options for seral console. Also provide a default
option of it being turned off instead of always selected.
Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac
Signed-off-by: Aaron Durbin <adurbin@chormium.org>
Reviewed-on: https://review.coreboot.org/13790
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Fix an error where a variable named 'free' was shadowing the
function 'free'.
src/lib/memrange.c:293:73: error: declaration of 'free' shadows a global
declaration [-Werror=shadow]
Change-Id: Ie57194b392f8f00ed4fd5c76dab27299b00ae293
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13788
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The used Baytrail-M SoC on TCU3 tend to have issues
with DisplayPort if the graphic power gate is not set up
in coreboot. To avoid this error, use the graphic init
code on this board.
Change-Id: I973bbaa7d86c1ede1f2884b3a08ccb31f7d85087
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13774
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On some devices it can happen that DisplayPort TX lanes
do not work properly if the power gate setup is omitted.
If that happens, DisplayPort training will fail and therefore
DisplayPort channel will not work. Both ports are affected.
It seems that not every CPU shows this effect
and those that are affected tend to fail more often in a cold
environment.
With this fix a board that originally shows this failure
was running for over 1000 power cycles without issues.
Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13743
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For C_ENVIRONMENT_BOOTBLOCK, memlayout.ld is added by call to
early_x86_stage. Remove redundant addition of memlayout.ld in this
case.
Change-Id: Ibb5ce690ac4e63f7ff5063d5bd04daeeb731e4d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/13777
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The missing braces for access to a union member
cause an error on gcc versions < 4.6.
Change-Id: I7de14a6d89219f5376f4f969adecfe8014a5a9d8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13776
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 17cb0370a7.
It’s the wrong thing to do, to just disable the warning. The code is
fixed for 32-bit user space now in Change-Id
I85bee25a69c432ef8bb934add7fd2e2e31f03662 (commonlib/lz4_wrapper: Use
correct casts to ensure valid calculations), so enable the warning
again.
Change-Id: I6d1c62c7b4875da8053c25e640c03cedf0ff2916
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13772
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Commit 09f2921b (cbfs: Add LZ4 in-place decompression support for
pre-RAM stages) breaks building cbfstool with gcc (Debian 4.9.2-10)
4.9.2 in Debian 8.3 (jessie) with a 32-bit user space. It works fine
in a 64-bit user space.
```
/home/joey/src/coreboot/src/commonlib/lz4_wrapper.c:164:18: note: in expansion of macro 'MIN'
size_t size = MIN((uint32_t)b.size, dst + dstn - out);
^
/home/joey/src/coreboot/src/commonlib/include/commonlib/helpers.h:29:35: error: signed and unsigned type in conditional expression [-Werror=sign-compare]
#define MIN(a,b) ((a) < (b) ? (a) : (b))
^
```
The problem is arithmetic on void*, so explicitly cast to the wanted
types as suggested by user *redi* in #gcc@irc.freenode.net.
Change-Id: I85bee25a69c432ef8bb934add7fd2e2e31f03662
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13771
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The builders run perl scripts in taint mode, and some of the checks
that the kconfig lint script were running were tainted, causing
the script to terminate early when running on the servers.
This checks to see if taint mode is enabled, and untaints the path
if it is. All external tools (git & grep) must be in
/bin, /usr/bin, or /usr/local/bin.
This also removes the check for unused kconfig files if taint mode
is enabled.
Change-Id: I8d1e1c32275f759d085759fb5d8a6c85d4f99539
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
When U-Boot isn't selected as a payload, two of the targets:
$(project_dir): and $(project_dir)/$(TAG-y) evaluated to the same
value, generating a make warning when running a clean. By adding
additional text to the file that is created, this is avoided.
Gets rid of these warnings:
Makefile.inc:54: warning: overriding commands for target `u-boot'
Makefile.inc:37: warning: ignoring old commands for target `u-boot'
Change-Id: I4b4df753612b674b3ccde2a757338840be92d1f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the documentation to add the minimal ACPI support. Also add
TempRamExit entry to the FSP features table.
TEST=None
Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
There was a report that xcompile wasn't finding the compilers correctly,
so to aid in future debugging, this adds a parameter to show what
xcompile is doing as it runs.
Run from the command line:
./util/xcompile/xcompile --debug
Change-Id: I779cb3de7b4e3f62a2ef2a6245c3538be518870c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It seems that the exact behavior of -Wsign-compare changes between GCC
versions... some of them like the commonlib/lz4_wrapper.c code, and some
don't. Since we don't have a well-defined HOSTCC toolchain this slipped
through pre-commit testing. Explicitly silence the warning to ensure
cbfstool still builds on all systems.
Change-Id: I43f951301d3f14ce34dadbe58e885b82d21d6353
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13769
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some users may wish to run this script using a coreboot image
that does get built in the usual build/ directory, for example
if abuild is used to generate the image.
Change-Id: I7e98780f8b7b57ebbf3babd6a289f0e4fd4103d8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/12489
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use shared gpio code from common folder.
Remove the now unused bd82x6x/gpio.c.
Needs test on real hardware !
Change-Id: Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13616
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.
Needs test on real hardware !
Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This turned out really handy when I tried to build coreboot
for my Chromebox.
These scripts can be used to extract System Agent reference code
and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a
Chrome OS recovery image.
crosfirmware.sh downloads a Chrome OS recovery image from the recovery
image server, unpacks it, extracts the firmware update shell archive,
extracts the firmware images from the shell archive.
To download all Chrome OS firmware images, run
$ ./crosfirmware.sh
To download, e.g. the Panther firmware image, run
$ ./crosfirmware.sh panther
extract_blobs.sh extracts the blobs from a Chrome OS firmware image.
Right now it will produce the ME firmware blob, IFD, VGA option rom,
and mrc.bin
Change-Id: I5fb7e14b10e03e18cd360bc35f1dc92e8ed34e63
Signed-off-by: Joe Pillow <joseph.a.pillow@gmail.com>
Reviewed-on: https://review.coreboot.org/13752
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Stefan Reinauer