With this change cbfs_boot_locate will check the RO (COREBOOT) region if
a file can not be found in the active RW region. By doing so it is not
required to duplicate static files that are not intended to be updated
to the RW regions.
The coreboot image can still be updated by adding the file to the RW
region.
This change is intended to support VBOOT on systems with a small flash
device.
BUG=N/A
TEST=tested on facebook fbg1701
Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all Rangeley SKUs have a fixed 100MHz BCLK.
As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0].
Using fixed BCLK was causing wrong values of core frequencies in _PSS table
for SKUs that do not have BCLK=100MHz.
Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f
Signed-off-by: Hannah Williams <hannah.williams@dell.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus. This romstage variant allows for reading the SPD data over
SMBus.
V.2: Dispence with memcpy().
V.3: Revert back to previous patch with memcpy().
V.4: Rewrite again to avoid memcpy().
BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous values do not affect the touchscreen function. But, the
previous values cause the power leakage in S0ix.
from b/142368161:
1. Modify GPP_D: The specification define T1 >= 10ms. We change it to
12ms for a safety and low impact value in our mind. Enable pin as
GPP_D9 is define to be AVDD in specification. Set it to 10ms to
make it to be the final one to pull low during power off sequence .
2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we
got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be
500us . So we change it to 5 to be a low impact value in our mind
according to the true T4 value we got .
BUG=b:142368161
BRANCH=Master
TEST=emerge-hatch coreboot chromeos-bootimage
./util/abuild/abuild -p none -t google/hatch -x -a
Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Output file is used only as a debugging aid.
Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is a property of the FSP, not something the user can decide.
Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
postcar stage does not consume cpulib.c, so don't include it there.
Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Drallion can be either a clamshell or convertible depending on the
presence of the 360 sensor board. Set the smbios type 3 enclosure type
to either CONVERTIBLE or LAPTOP accordingly.
BUG=b:143701965
TEST='dmidecode -t 3'
Type = Convertible with sensor board connected
Type = Laptop with sensor board disconnected
Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36512
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a single function to determine if the 360 sensor board is present
on a device.
BUG=b:143701965
TEST='emerge-drallion coreboot'
Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Only FIT payloads provide their own FDT.
Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36599
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's only used for romstage and is incompatible to ramstages. The latter
get `cbmem_top` passed as a third argument now.
Also drop comments that don't apply to this file anymore.
Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus.
BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared
between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any
other guard to assign FSP_TEMP_RAM_SIZE.
Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update thermal threshold settings for TSR3 sensor. There is an issue
fan is always running, even during system idle state. This change
fixes this issue and fan starts only when it breaches the temperature
threshold.
BRANCH=None
BUG=b:143861559
TEST=Built and tested on Helios system
Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The quotes were not stripped for the cbfs filenames of the FSP
components. This is causing problems when the regions-for-file macro is
executed (when VBOOT is enabled and the files should be filtered).
BUG=N/A
TEST=build
Change-Id: I14267502cfab5308d3874a0c0fd18a71b08bb9f8
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36548
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When prog_locate() is called in the stage VBOOT is starting from and the
image to be loaded is not the target image vboot_prepare() may be called
too early.
To prevent this vboot_prepare() is removed from the vboot_locator
structure. This allows more control over the start of the vboot logic.
To clarify the change the vboot_prepare() has been renamed to
vboot_run_logic() and calls to initialize vboot have been added at the
following places:
postcar_loader: when VBOOT starts in ROMSTAGE
romstage_loader: when VBOOT starts in BOOTBLOCK
ramstage_loader: when VBOOT starts in ROMSTAGE
BUG=N/A
TEST=tested on facebook fbg1701
Change-Id: Id5e8fd78458c09dd3896bfd142bd49c2c3d686df
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36543
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align the eltan mboot support with coreboot tpm support to limit the amount of custom code.
We now only support SHA256 pcrs, only single a single digest will be handled in a call.
The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is
selected.
BUG=N/A
TEST=tested on fbg1701
Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Use __builtin_offsetof (which is treated as a constant expression) with
Clang & GCC. This also allows check_member to work with Clang 9.
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced in recent SMM region handling overhaul.
Previously IED region size was hardcoded in the code. However when
chip code was modified to use smm_region() and friends, IED_SIZE
define was not added and build system quetly substituted it with 0.
Also, drop CONFIG_SMM_TSEG_SIZE which is now obsolete.
TEST=tested on watson platform; without the patch tg3 NIC driver doesn't work
properly and that gets solved with this patch
Change-Id: Id6fb258e555bb507851886b0e75f1f53c3762276
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36417
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if
CONFIG_MMCONF_BASE_ADDRESS is not defined.
Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35883
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though the vendor firmware enables the i8042 I/O port, it doesn't
feed valid data to those, but instead uses USB HID devices.
Disable the KBC port in SuperI/O and report no KCS port using FADT.
Fixes:
* Fixes error message in Linux that i8042 keyboard couldn't be enabled.
Tested on Supermicro X11SSH-TF:
The virtual remote managment console still works.
Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Note that due to UNKNOWN_TSC_RATE, each stage will have
a slow run of calibrate_tsc_with_pit(). This is easy enough
to fix with followup implementation of tsc_freq_mhz() for
the cpu.
Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_FSP_CAR should not be a user visible option, but depends on the
choice presented in the soc Kconfig.
This also removes the dependencies on ADD_FSP_BINARIES. You need to
included those for other stages too so there is no need to make this
requirement explicit for FSP-T.
Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is done in postcar stage. This also assumes CAR tear down will
always be done in postcar stage.
Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tune stapm percentage from 80 to 68 and time from 250 second
to 90 second make them meet Lenovo temperature spec.
BUG=b:143859022
TEST=build firmware and install it to DUT and run fishbowl 1000,
check temperature whether meets spec.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Removes unnecessary information about the Ring Sliced VR configuration
from another board with FSP1.1 (which is no longer supported).
Change-Id: Ia2b90d9ede782852c2127da972333bada378b217
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D
SuperIO, dropping the need to include code from the superio.asl, which
was inherited from another chip (NCT6776) and required fixes. SSDT gen
support for Nuvoton NCT6791D chip was added in the previous patch [2].
[1] https://review.coreboot.org/c/coreboot/+/33033
[2] https://review.coreboot.org/c/coreboot/+/36379
Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Internal/external displays functional on all variants
other than Samus. Unable to verify external outputs on
Samus (USB-C using DP/HDMI adapter).
Test: build/boot lulu variant with libgfxinit, verify internal/
external displays functional prior to OS display driver loaded.
Both linear framebuffer and scaled VGA text modes functional.
Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus
move them to common code.
Tested successfully on X11SSM-F
Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of doing our own calculations, rely on TOLUM returned by FSP
for cbmem_top. This (hopefully) saves us from making mistakes in weird
calculations of offsets and alignments.
Further this makes it easier to implement e.g. SGX PRMRR size selection
via Kconfig as we do not have to make any assumptions about alignments
but can simply pass (valid) values to FSP.
Tested successfully on X11SSM-F
Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wim Vervoorn