Commit graph

330 commits

Author SHA1 Message Date
Richard Spiegel
12c12d1e07 soc/amd/stoneyridge/include/soc/smi.h: Fix name collision
When smi.h is included to southbridge.h (to use SCI/SMI definitions within
southbridge.h definitions), this causes a collision of the definition of NONE
(ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt
types (SCI/SMI), add INTERRUPT_ at the start of each definition.

This is preparation to have GPIO table/code also declare/program SCI/SMI.

BUG=b:72875858
TEST=Build grunt.

Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25845
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27 09:24:37 +00:00
Marc Jones
4c887eaeba soc/amd/stoneyridge: Enable CMOS VBNV backup to flash
Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.

BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.

Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27 09:13:31 +00:00
Richard Spiegel
2d72a17058 soc/amd/common/block/include/amdblocks/psp.h: Replace todo message
It was decided to not add the buffers definitions, so the todo message
is obsolete. Replace it with minimum instructions about when a new buffer
will be needed.

It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is
about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO.

BUG=b:77940747
TEST=None.

Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25740
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26 22:00:56 +00:00
Daniel Kurtz
225b03534c soc/amd/stoneyridge: Fix smi_write32 arg order in disable_all_smi_status
The argument order for smi_write32() is offset, value.  Current code had
it backwards.

So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.

BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.

Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-26 06:58:27 +00:00
Daniel Kurtz
963419a312 soc/amd/stoneyridge: Static constify smi_sources
smi_sources is a file local array of constants.

Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26 06:57:58 +00:00
Marc Jones
cfb1680a88 soc/amd/stoneyridge: Add additional early LPC and SPI init
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.

BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.

Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-25 14:11:37 +00:00
Richard Spiegel
f35cc4d60f soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory access
Found-by: Coverity (CID 1387031: Memory - illegal accesses
(BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of
19 bytes on destination array "dimm->module_part_number" of size 19 bytes
might leave the destination string unterminated. Fix the size parameter.

BUG=b:76202696
TEST=Build and boot kahlee, using special debug code to see the output
strings, which was later removed.

Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24 17:14:29 +00:00
Aaron Durbin
6403167d29 compiler.h: add __weak macro
Instead of writing out '__attribute__((weak))' use a shorter form.

Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24 14:37:59 +00:00
Aaron Durbin
851dde8255 drivers/spi: reduce confusion in the API
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:

- Remove spi_xfer_two_vectors() which was fusing transactions to
  accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
  utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
  will trigger an error as these controllers can't support the api.

[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html

Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-23 20:58:58 +00:00
Patrick Rudolph
e56189cfd1 pci: Move inline PCI functions to pci_ops.h
Move inline function where they belong to. Fixes compilation
on non x86 platforms.

Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20 13:03:54 +00:00
Richard Spiegel
6fcb9b00c8 soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.

BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.

Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20 13:03:14 +00:00
Richard Spiegel
51895d1838 soc/amd/common/block/pi/heapmanager.c: Simplify code
There are sections of code that are almost identical and they can be
converted to auxiliary procedures. For allocating heap, 3 sizes (the
buffer size of currently being examined node, the buffer size of the
current best fit node and the minimum size for a buffer that will need
to be split if selected as the best fit) are used often so they could
be stored in temporary variables. These 2 changes will make code shorter,
with less indentation problems and overall easier to read. The actual
logic of the code is not changed.

BUG=b:77940747
TEST=Build and boot grunt.

Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25703
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19 15:05:08 +00:00
Richard Spiegel
08c4ce851e soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code reference
With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.

BUG=b:77999987
TEST=Build and boot grunt.

Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18 09:54:45 +00:00
Richard Spiegel
3d34ae3fc4 soc/amd/stoneyridge/northbridge.c: Fix bit definitions
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.

BUG=b:77940747
TEST=Build and boot grunt.

Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 08:44:50 +00:00
Richard Spiegel
bbcfa8afd5 soc/amd/stoneyridge/lpc.c: Fix bit definitions
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.

BUG=b:77940747
TEST=Build and boot grunt.

Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:44:44 +00:00
Martin Roth
2c3e3ef654 soc/amd/stoneyridge: add a romstage hook for mainboards
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage.  This adds an early call for configuration
and passes along whether the system is currently resuming from S3.

BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.

Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-13 16:50:41 +00:00
Raul E Rangel
99f54a60bf include/memory_info.h: Change serial number field from 5 bytes to 4
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.

This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.

There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
  it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
  decoding the serial number into a byte array.

google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.

Testing this on grunt, dmidecode now shows the full serial number:
        Serial Number: 00000000

BUG=b:65403853
TEST=tested on grunt

Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-12 15:21:45 +00:00
Raul E Rangel
1f54e9571e soc/amd: Fix generating SMBIOS Type 17
The converter was setting SMBIOS values when dimm_info expects SPD
values.

dmidecode now shows the following:
Memory Device
        Array Handle: 0x0000
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 8192 MB
        Form Factor: SODIMM
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous
        Speed: 933 MT/s
        Manufacturer: Hynix/Hyundai
        Serial Number: 00000000
        Asset Tag: Not Specified
        Part Number: HMAA51S6AMR6N-UH
        Rank: 1
        Configured Clock Speed: 933 MT/s
        Minimum Voltage: Unknown
        Maximum Voltage: Unknown
        Configured Voltage: Unknown

Example debug output:
AGESA TYPE 17 DMI INFO:
  Handle: 1
  TotalWidth: 64
  DataWidth: 64
  MemorySize: 8192
  DeviceSet: 0
  Speed: 1200
  ManufacturerIdCode: 44416
  Attributes: 1
  ExtSize: 0
  ConfigSpeed: 933
  MemoryType: 0x1a
  FormFactor: 0xd
  DeviceLocator:   DIMM 0
  BankLocator:  CHANNEL A
  SerialNumber(8): ' 00000000'
  PartNumber(20): 'HMAA51S6AMR6N-UH    '
CBMEM_ID_MEMINFO:
  dimm_size: 8192
  ddr_type: 0x1a
  ddr_frequency: 933
  rank_per_dimm: 1
  channel_num: 0
  dimm_num: 0
  bank_locator: 0
  mod_id: 44416
  mod_type: 0x4
  bus_width: 3
  serial: 0x00000000
  module_part_number(18): 'HMAA51S6AMR6N-UH  '

The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.

`mosys memory spd print all` is still failing though. I will look into
that next.

BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above

Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 17:21:16 +00:00
Jonathan Neuschäfer
73cd7cf0f2 src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts")
Change-Id: I5730259bc6819defc482d31644e1f476679257b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25588
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 14:18:35 +00:00
Marshall Dawson
8f031d8234 amd/stoneyridge: Reorder temp mtrr for flash
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init.  The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores.  The ranges need to be
the correct calculated values and not some temporary setting.

This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit.  MTRRs within a CU are shared
so the AP always stays in sync.

BUG=b:77457944
TEST=run on Kahlee

Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 14:13:56 +00:00
Richard Spiegel
6d61db0d2c soc/amd/stoneyridege: Create AP jump structure
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.

BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.

Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10 17:09:22 +00:00
Richard Spiegel
09a16e6a32 soc/amd: Add "halt this AP" callback to romstage
As part of moving AGESA calls from bootblock to romstage, callback function
AGESA_HALT_THIS_AP must be available at romstage.

BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.

Change-Id: I0992b2de5856881c19191ec4f637168727686524
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25527
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10 16:24:20 +00:00
Marc Jones
d6a82007bd amd/stoneyridge: Add GNB IOAPIC init
Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.

BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.

Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09 09:41:47 +00:00
Marshall Dawson
1dd7a11ec4 amd/common/block/pi: Make agesa_heap_base() static
Convert agesa_heap_base() to static since it's unused outside of
heapmanager.c.

Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-06 06:44:18 +00:00
Marshall Dawson
d85c4afea5 amd/stoneyridge: Use defined value for SPI flash MTRR
Replace an absolute value with a #define value in bootblock.  This is
in preparation for using an additional MTRR in a subsequent patch.

Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-06 06:43:43 +00:00
Richard Spiegel
8e1f563cd6 mb/amd/gardenia/gpio.c: Convert GPIO to new format
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.

BUG=b:72875858
TEST=Build Gardenia.

Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05 15:57:03 +00:00
Martin Roth
d738749d47 src/soc/stoneyridge: Add a check for CMOS failure
BUG=b:77345148
TEST=Pull power from grunt, verify CMOS power failure is detected.
Reboot and verify that CMOS power failure is not detected.

Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-02 21:03:34 +00:00
Raul E Rangel
80d042c467 soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect values
Example output:
AGESA TYPE 17 DMI INFO:
  Handle: 1
  TotalWidth: 64
  DataWidth: 64
  MemorySize: 8192
  DeviceSet: 0
  Speed: 1200
  ManufacturerIdCode: 44416
  Attributes: 1
  ExtSize: 0
  ConfigSpeed: 933
  MemoryType: 0x1a
  FormFactor: 0xd
  DeviceLocator:   DIMM 0
  BankLocator:  CHANNEL A
  SerialNumber(8):  00000000
  PartNumber(20): HMAA51S6AMR6N-UH

CBMEM_ID_MEMINFO:
  dimm_size: 0
  ddr_type: 0x1a
  ddr_frequency: 1200
  rank_per_dimm: 1
  channel_num: 0
  dimm_num: 0
  bank_locator: 0
  mod_id: 44416
  mod_type: 0x1a
  bus_width: 64
  serial(4): 0000
  module_part_number(23): HMAA51S6AMR6N-UH   ��@

dimm_size, mod_type, bus_width need to be updated so they return the
correct values. module_part_number is missing a null terminator due to
the AGESA part number being larger than the dimm_info buffer.

Example dmidecode output:
Memory Device
        Array Handle: 0x0000
        Error Information Handle: Not Provided
        Total Width: 8 bits
        Data Width: 8 bits
        Size: No Module Installed
        Form Factor: Unknown
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous
        Speed: 1200 MT/s
        Manufacturer: Hynix/Hyundai
        Serial Number: 0000
        Asset Tag: Not Specified
        Part Number: HMAA51S6AMR6N-UH
        Rank: 1
        Configured Clock Speed: 1200 MT/s
        Minimum Voltage: Unknown
        Maximum Voltage: Unknown
        Configured Voltage: Unknown

To enable the output set CONFIG_DEBUG_RAM_SETUP.

The Kconfig change is required in order to enable
CONFIG_DEBUG_RAM_SETUP, otherwise it's not a valid option.

BUG=b:65403853
TEST=Test output shown above

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eac00b9400056357915761287770a400b3f9f8b
Reviewed-on: https://review.coreboot.org/25303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23 15:33:27 +00:00
Marshall Dawson
70f051f236 amd/stoneyridge: Add PM1 wake status to boot log
Print the wake status bits to the console.  The format is kept similar
to Intel's to maintain compatilibity with inspection utilities.  Add
relevant wake events from the register to the ELOG.  Clear the register
before continuing.

TEST=Inspect console and ELOG for Grunt
BUG=b:75020968

Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-03-22 09:01:03 +00:00
Richard Spiegel
6dfbb59307 soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So  configure_stoneyridge_uart()
became redundant. Remove procedure  configure_stoneyridge_uart().

BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.

Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19 14:19:46 +00:00
Garrett Kirkendall
64294eb5e2 soc/amd/stoneyridge: Call sb_spibase() early
Call sb_spibase() early so that it will set up the SPI base address.
This is another step to moving AGESA calls out of the bootblock.

BUG=b:74427893
BRANCH=master
TEST=Build and boot Grunt.

Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-17 16:32:15 +00:00
Richard Spiegel
a9f49366c0 soc/amd/stoneyridge: Create a HALT_THIS_AP callout
It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.

BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.

Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-16 19:01:46 +00:00
Richard Spiegel
0e0e93cce1 soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
Devices that need to have their AOAC register enabled do have a delay before
they become available. Currently each device has their own wait loop. Create
a procedure that initializes all AOAC devices in a table and wait for all
AOAC to become alive, then call this new procedure before the call to
initialize the UART. Then change all procedures that initialize some AOAC by
moving the devices to the table and removing AOAC initialization code.

BUG=b:74416098
TEST=Build and boot kahlee checking that UART is sending debug messages out.

Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-16 15:24:44 +00:00
Garrett Kirkendall
e7513e0d5c soc/amd/stoneyridge: Call sb_acpi_mmio_decode()
Call function sb_acpi_mmio_decode() from bootblock_fch_early_init().
This enables decoding of the FCH ACPI MMIO regions 0xfed80000 -
0xfed81fff.  This is another step to moving AGESA out of the bootblock
for StoneyRidge

BUG=b:74586747
BRANCH=master
TEST=Build and boot on Grunt.

Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25161
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-15 15:45:58 +00:00
Garrett Kirkendall
6575306663 soc/amd/stoneyridge: Configure FCH for TPM
In preparation for moving AGESA calls out of the bootblock:
* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy
TPM IO 0x7f-0x7e and 0xef-0xee
* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.

BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)

Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-14 11:17:11 +00:00
Garrett Kirkendall
8da81da3b9 soc/amd/stoneyridge: Add function to enable I2C host controllers
In preparation for moving AGESA calls out of bootblock:
Add function to enable the four stoneyridge I2C engines.

BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)

Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09 17:12:15 +00:00
Garrett Kirkendall
9858bd2e3d soc/amd/stoneyridge: Add ACPI MMIO enable function
In preparation for moving AGESA calls out of bootblock:
* Add definitions for needed registers in southbridge.h
* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to
  0xfed81ffff.  Will be called by a later commit.

BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build boot Grunt (with other changes
to call code not committed at this time)

Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25025
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09 17:11:20 +00:00
Richard Spiegel
6a3891404c soc/amd/stoneyridge/Kconfig: Create a power restore option
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.

BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).

Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07 21:21:26 +00:00
Garrett Kirkendall
a0ff6fc860 soc/amd/stoneyridge: clean up southbridge.c
* Limit dependency on vendorcode header files and use defines from
  iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.

BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07 17:55:12 +00:00
Garrett Kirkendall
d255830418 soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnb
Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h
and southbridge.h

BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07 17:55:00 +00:00
Garrett Kirkendall
050b6fb125 soc/amd/stoneyridge: Add southbridge definitions
* Add definitions to iomap.h for AMD ACPI MMIO base addresses.
* Add FCH AOAC registers for enabling FCH devices.
* From: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h,
  Models 70h-7Fh Processors Rev 3.04

BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/24998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07 17:54:47 +00:00
Martin Roth
069ca66ea4 soc/amd/stoneyridge: Add ST/CZ SMBus device id
The SMBus PCI device ID for Stoney wasn't updated when the code was
pulled over from hudson.  This means that the IOAPIC wasn't being
initialized in coreboot.

BUG=b:74070580
TEST=Boot Grunt, see IOAPIC init messages in console.

Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/24930
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06 08:45:32 +00:00
Justin TerAvest
bb75effd87 soc/amd/stoneyridge: Remove printk for GPIO
The printk() calls in sb_program_gpios() aren't necessary, and incur a
13 second delay if the function is called from
bootblock_mainboard_early_init(). This commit removes them so GPIOs can
be set up earlier.

TEST=call sb_program_gpios from bootblock_mainboard_early_init
BUG=b:73898539

Change-Id: I064291decf47d86132e36469e029b3262ec20172
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 16:05:18 +00:00
Marc Jones
5fd1d5ad12 soc/amd/stoneyridge: Refactor northbridge resource allocator
The resource allocator was overly complicated due to porting
from a multi-node resource allocator. It had some assumptions
about the UMA memory and where it would be located. The
refactored allocations account for UMA being reserved above 4GiB.

TEST=Check CBMEM table has correct RAM regions.

Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 18:18:21 +00:00
Marc Jones
932b5bdb6d soc/amd/common: Save the UMA settings from AGESA
Save the UMA base and size settings returned by AGESA
in amdinitpost();

Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 18:18:07 +00:00
Richard Spiegel
99fd08d324 soc/amd/common/block/pi/amd_late_init.c: Fix part number
Kahlee DIMM have invalid string when it comes to part number
(bytes 0x149-0x15c). We currently force a NA string, but grunt has the
proper strings. Just let the string go through, and a second commit
within smbios.c will be responsible for testing the string and taking
proper action.

BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Remove string injection before
committing.

Change-Id: I427262873f9ec80f459245e5f509e28a68de3074
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 15:06:36 +00:00
Justin TerAvest
bf0a67f3ee soc/amd/stoneyridge: Add readable macros for GPIO
This commit defines a set of macros for defining GPIO configuration that
are easier to read than the raw iomux function values used today.

TEST=None
BUG=b:72875858

Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22 16:35:10 +00:00
Chris Ching
2269a3c328 soc/amd/stoneyridge: Add functions for GPIO interrupts
Add a function to configure interrupt settings for a GPIO.  This does
not currently configure GEVENT signals.

The second function returns the GPIO interrupt status and clears the
flag if set.

BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt

Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21 23:36:11 +00:00
Marc Jones
fa650f5e8c soc/amd/stoneyridge: Add UMA save function
Save the UMA values from AGESA to use in resource
allocation in ramstage.

Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23817
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-21 16:08:45 +00:00
Jonathan Neuschäfer
5268b76801 src/soc: Fix various typos
These typos were found through manual review and grep.

Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 23:17:39 +00:00