Use bitwise or instead of additions to build bit masks with multiple
bits set.
TEST=Timeless build results in identical image on amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add documentation describing how to add support for a new memory
technology to spd_tools:
- Add a section to the README.
- Document the memTech interface in spd_gen.go.
BUG=b:191776301
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16
of the misc I2C pad control registers is defined as BiasCrtEn, so rename
I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set RFI Spread Spectrum to 6% for Redrix as RF team request.
The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.
BUG=b:200886627
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.
BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
For the Qualcomm PBL configuration of GPIO, we need to initial the
GPIOs for VDD33# and RST# at the beginning of coreboot. According to
the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#.
BUG=b:204637643
BRANCH=trogdor
TEST=verified the waveform of ps8640 at coreboot phase.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns
and fall_time_ns values for each port are capured by a scope.
BUG=None
BRANCH=dedede
TEST=built and verified adjusted I2C speed < 400KHz
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add ELAN touchscreen support for magneto.
BUG=b:203122673
TEST=Build and verify that touchscreen works.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update charger performance control table of DPTF for bugzzy.
Since the EC change chromium:197776876 modified maximum charging current
to reduce skin temperature, this change adjusts the charging performance
table with the modified value.
BUG=b:197776876
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
GNVS should not be used for values that are static at runtime. Thus,
use SSDT for the SGX fields.
Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update list of boards that support vboot.
Change-Id: Id5d4d18202bf85c5ba407efd690eee5cba88a8a7
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58975
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This drops VBOOT_NO_BOARD_SUPPORT.
There is little impact of always having recovery_mode_switch()
implemented in bootmode.c. A weak write_protect_state() is not
necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation.
Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS)
so the weak implementation would not be referenced.
Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This error prevented the last line of the Kconfig tree from being
printed or added to the output file. This is a significant problem if
you try to use the generated file as the kconfig source, because it
changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to
NO. This causes the build to stop working.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is no platform in our tree that requires the PCI MMIO ops but
doesn't want the pci_s_* definitions. The only case where we include
the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to
use MMIO is on older x86 platforms, so move the guard there.
Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Avoid indirect <vc/google/chromeos/chromeos.h> as the
files really only need <security/vboot/vboot_common.h>.
Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Technically, it's not depending on the hardware but on the software
(OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A
support disabling of the PM Timer, when the respective FADT flag is
unset. Thus, drop this guard.
For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the
Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`.
As of this change, new platforms must either implement code for
disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such
is present.
Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This option will allow setting the FSP alignment in CBFS.
BUG=b:179699789
TEST=Boot with and without the option set and verify -a option was
passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We no longer need to do this since we relocate at runtime.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD platforms pass in the base address to cbfs tool:
fspm.bin-options: -b $(CONFIG_FSP_M_ADDR)
There is no technical reason not to allow FSP-M to be relocated when
!XIP. By allowing this, we no longer need to pass in the base address
into cbfstool when adding fspm.bin. This enables passing in the
`--alignment` argument to cbfs tool instead. cbfstool currently has a
check that prevents both `-b` and `-a` from being passed in.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was
derived by examining the `cbfstool print` output and summing the files
we intend to preload.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add the parts below which will be used by the brya variant Vell. Add
the parts to memory_parts.json and generate the SPDs using spd_gen.
Micron MT62F512M32D2DR-031 WT:B
Micron MT62F1G32D4DR-031 WT:B
Hynix H9JCNNNCP3MLYR-N6E
Generated using:
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
BUG=b:204284866
TEST=None
Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Read fw_config value from VPD.
This new option can be used where chrome EC is not supported like
pre-silicon platform and fw_config can be updated by VPD tool in OS.
TEST= boot to OS and read fw_config from vpd
1. Boot to OS
2. Write "fw_config" in VPD
ex) vpd -i "RW_VPD" -s "fw_config"="1"
3. reboot and check fw_config value from coreboot log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Request fw_config values from various sources (as enabled via Kconfig)
until a valid value has been read.
With this change, Chrome EC CBI takes precedence over CBFS fw_config.
TEST=select both configs and check fallback behavior.
1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS
2. check log for reading fw_config from CBI and CBFS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
elog init requires doing a lot of SPI transactions. This change makes it
clear how long we spend initializing elog.
BUG=b:179699789
TEST=Boot guybrush and see elog init timestamps
114:started elog init 3,029,116 (88)
115:finished elog init 3,071,281 (42,165)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58957
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This gives us a knob that can be controlled via a .config to
enable/disable file preloading. I left the option disabled because
there is currently a race condition that can cause data corruption when
using the SPI DMA controller. The fix will actually introduce a
boot time regression because the preloads are happening at the same time
as the elog init. I want to keep preloading disabled for now until
I get all the sequencing worked out.
BUG=b:179699789
TEST=Boot guybrush and verify no preloading happens.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This adds the following commits from the submodule:
* cezanne: Upgrade blobs to 1.0.0.5
* cezanne: Upgrade ABL to ver. 0x19036070
* cezanne: Upgrade SMU FW to 64.52.0
* cezanne: Upgrade SMU to 64.57.0
* cezanne: Update ABLs to 0x1A296070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id7b3f5d38d34c2714548dff92b7b83fb2628e936
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58989
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPI speed override is not related to ChromeOS, thus the
location in chromeos.c was poor choice.
Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Most of the System76 boards have now been merged.
Change-Id: I0353b28c1df3da8be961cb43225dcf9e30b47d16
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Since all other defines for the number of certain things are at the top
of the file, move NUMBER_SMITYPES there as well to keep things
consistent.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap
returns early when the scimap is greater or equal than SCIMAPS, so for
SMITYPE_ACDC_TIMER it returned early without doing what was expected
from it to do despite that being a valid value, so fix this off-by-one.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Return 0 instead of -1 in case of error. Both values indicate an error
has happened. Adapt `cpu_bus_scan()` accordingly.
Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
EINT event mask register is used to mask EINT wakeup source.
All wakeup sources are masked by default. Since most MediaTek SoCs do
not have this design, we can't modify the kernel EINT upstream driver to
solve the issue 'Can't wake using power button (cros_ec) or touchpad'.
So we add a driver here to unmask all wakeup sources.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Felix Held