Commit Graph

55085 Commits

Author SHA1 Message Date
Matt DeVillier 132783baf8 Update amd_blobs submodule to upstream main branch
Updating from commit id 68ebd4b567f4 (2023-11-27):
  PCO: Update ABL to version CABLRV21080200

to commit id eb91266f01db (2023-11-29):
  MDN: Update mendocino SMU to 90.43.0

This brings in 1 new commit:
eb91266f01 MDN: Update mendocino SMU to 90.43.0

Change-Id: Iebc3d0ffe9874a84cac9cafc7b7b3514d251e4a5
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79315
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 16:10:28 +00:00
Arthur Heymans ea2e210548 soc/amd/genoa: Implement romstage
The only thing romstage needs to do is find cbmem_top.

TESTED: reaches ramstage.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic2837c4a2b0ec8dcd9dd99602f9c073999c36139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76514
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30 15:18:45 +00:00
Arthur Heymans 98a46fb2dd vendorcode/amd/opensil: Implement cbmem_top_chipset
Use an xPRF call to get the top of lower DRAM.

Organize Makefile to keep romstage/ramstage components separate.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30 15:16:47 +00:00
Julius Werner 63ad72db6c Update vboot submodule to upstream main
Updating from commit id f2b01bf0:
2023-10-27 Julius Werner   firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY

to commit id ba7fd22d:
2023-11-27 Julius Werner   Makefile: Always link libdl

This brings in 54 new commits:
ba7fd22d Makefile: Always link libdl
1b30d195 sign_official_build: sign_update_payload with pkcs11
ca7a1427 sign_firmware: support loem key config
a9623573 sign_official_build: add keys to default key config
d41497dc sign_official_build: support loem key config
da2450db sign_official_build: support sign with .vbprik2 files
ee326142 getversion: Make reproducible
8aaf9e32 futility: fix a typo in help message of `read`
9ce505f4 futility: Fix incorrect warning about signing length
23a0ce4e scripts: add lib/keycfg.sh
2e34330b Makefile: Fix firmware build for FIRMWARE_ARCH=arm64
fd5937d1 tests/futility/test_show_and_verify: Add test cases for invalid data key
00aa0626 futility/cmd_vbutil_kernel: Drop --pad option for --verify
c661ab76 futility/cmd_show: Drop --pad option
c70511d7 tests/futility/test_show_and_verify: Add test cases for kernel vblocks
c9100f46 signer: Use compression flags stored in the metadata file
f1f3076f vboot: Add vb_keyb_from_private_key
c39a2fc1 host: support signing with pkcs11 key for vbprik2
c6d44076 vboot: merge reading function of vb2/vb21 private key
6b8e759f vboot: replace custom prefix "pkcs11" to "remote"
481440d0 futility: Prefer to flash over CCD instead of C2D2
1244c06f futility/cmd_dump_fmap: Print an error if FMAP header not found
cab69289 futility/cmd_show: Fix parseable output for kernel preamble flags
71a03dc6 futility/cmd_show: Make preamble parseable output consistent
bdac62a4 futility/cmd_show: Make 'show' return 0 for invalid kernel body
135df2d7 futility/cmd_show: Show parseable "keyblock::valid" for valid keyblock
37f37fcd futility/cmd_show: Fix output for firmware body signature
79c244ff tests/futility/test_show_and_verify: Add test cases for bios_brya_mp.bin
d4b6560f signer: Update mkfs.erofs pcluster value to 32K
f79a2432 futility/cmd_sign: Fix a space in usage text
a307fcb5 futility: updater: rename --ccd to --ccd_without_servod
6b9f66d3 futility: updater: Fix malloc overflow due to broken keyblock
a94a784c updater: update: Support multiple Servos without --servo_port
25875bef tests/futility: Add test cases for VBOOT_CBFS_INTEGRATION
5f8e3973 futility/cmd_show: Fix typo "metatadata"
9d30a01f futility: Trim trailing spaces in kernel config
c59794a6 sign_uefi: Support signing via pkcs11
68d4aa4b sign_uefi: Skip private key check if it's a pkcs11 URI
6b9d624b sign_uefi: Pass each key path separately
483f65e4 sign_official_build.sh: properly show errors on loem issues
516ee7bc sign_uefi: Use named args instead of positional
0eec8e25 vboot_reference-sys: Switch from Command to bindgen::Builder
46f5aab8 image_signing: support multiple release names
f13af139 sign_official_build: Sudo invocation within bits of android signing
3f165374 futility: updater: Add optional serial number argument to --ccd
64379cc6 sign_official_build: add --debug flag
7160bf9f 2lib: Fix relocation issue when compiling locally with musl libc
0e27cdff vboot_reference-sys: Add vboot_host.h
2c82e73c Override use_apksigner FLAGS
b43469c7 futility/cmd_show: Support --publickey FW_VBLOCK
0eb4da96 tests/futility: Update kern_preamble.bin as kernel_part.bin
68a03355 tests/futility: Move test_show_vs_verify.sh into test_show_and_verify.sh
8daf1474 tests/futility: Move 'futility show' tests to a separate file
34190e3d futility: Exit with error when metadata hash verification not supported
967aa462 firmware/2lib: Fix function comment for vb2api_get_firmware_size()

Change-Id: I58b231d53f433a396b1ea8cd4e0ddc49a310e385
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79313
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-11-30 15:08:50 +00:00
Yidi Lin a9a8b5e36c Update arm-trusted-firmware submodule to upstream master
Updating from commit id 88b2d8134:
2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration)

to commit id e7486343d:
2023-11-28 22:48:16 +0100 - (Merge changes from topic "xlnx_fitimage_check" into integration)

This brings in 451 new commits.

Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-30 15:08:01 +00:00
Yidi Lin fe73a0e7b1 mb/google/corsola: Use fw_config to differentiate audio amps
Use fw_config to differentiate audio amps instead of the
kconfig option.

BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console

Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:07:16 +00:00
Robert Chen 508296333b mb/google/nissa/var/quandiso: Add LTE only daughterboard support
Quandiso does not use DB_1C, replace the fw_config with LTE only
daughterboard.

BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:06:27 +00:00
Matt DeVillier 22ac6f6b2c mb/google/galdos/var/lars: Implement touchscreen power sequencing
Since lars has two touchscreen options, we need to determine which (if
any) are present on a given device at runtime so that there are not
multiple ACPI touchscreen devices (as it makes Windows unhappy).
Implement power sequencing and runtime detection for both touchscreen
options.

TEST=build/boot Win11/Linux on google/lars, verify touchscreen detected
and functional under both OSes.

Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30 15:05:42 +00:00
Matt DeVillier 0733ee6514 mb/google/glados/var/lars: Add Melfas touchscreen
LARS has a Melfas touchscreen option, so add an entry for it. Adapted
from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f
("Chell: Update DPTF parameters for CPU").

TEST=build/boot Linux on google/lars with Melfas touchscreen, verify
functional.

Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:05:05 +00:00
Werner Zeh 722c0b7b21 mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.

On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.

This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.

Test=Boot into Linux and make sure a write access into the EEPROM is
possible.

Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-11-30 15:03:33 +00:00
Weimin Wu fd1c2f488f mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device
Enable MIPI camera for anraggar project.

Sensor: OV13B10-GA5A
Driver: DW9714V
EEPROM: GT24P64E

Ref to SCH, use MIPI 4-lane serial output interface.

BUG=b:309518095
TEST=Google Camera app working

Checking log with:
coreboot log:
\_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h
\_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch
\_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h

kernel log:
kernel: [    6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1
cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom
cros_camera_service[4755]: Probing media device '/dev/media0'
cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17)
cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17

Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
2023-11-30 15:02:29 +00:00
Weimin Wu b667e27952 mb/google/nissa/var/anraggar: Enable CNVi Bluetooth
Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC,
and the relevant configuration needs to be modified in overridtre.cb.

BUG=b:304920262
TEST=lsusb
     ID 8087:0033 Intel Corp.
     rfkill list
     hci0:Bluetooth

Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:02:05 +00:00
Simon Yang ae2f046484 mb/google/nissa/var/anraggar: Tune eMMC DLL values
Anraggar cannot boot into OS and kernel loading failure.
Update eMMC DLL values to improve initialization reliability

- Sending different speed TX/RX command/data signal to eMMC and check
  the response is success or not.
- Collecting every eMMC that use for the project
- Based on above result to provide a fine tune DLL values

BUG=b:308366637
TEST=Cold reboot stress test over 2500 cycles

Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30 15:01:43 +00:00
Arthur Heymans 0832e6790d vendorcode/amd/opensil/genoa: Implement console callback
OpenSIL has an API to call back into the host firmware to print to the
console.

These could be moved to a common directory when there are more openSIL
implementations to see if it is actually common.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30 15:00:42 +00:00
Daniel Peng 49d1cf9d49 mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance.

The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W).

BUG=b:312321601
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
     Built and booted into OS, and confirm MSR PL1=17W correctly.

Change-Id: If7874d26038118c5605cf0721c30e681b45123fe
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 08:14:19 +00:00
Subrata Banik 38ab95ba5a mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION config
This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the
Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards
to retrieve the ISH version and store it into memory.

Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms
with ISH support (DRIVERS_INTEL_ISH).

Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config
selection for the Nissa baseboard is no longer needed.

BUG=b:280722061
TEST=Able to build and boot google/marasov.

Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-30 05:55:56 +00:00
Kun Liu f281de82a7 mb/google/rex/var/screebo: Change GPP_B14 from NC to NF
Change GPP_B14 from NC to NF

BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal

Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-29 15:15:14 +00:00
Shelley Chen ea9248e9fb mb/google/brox: Fix configuration for TPM
On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to
reflect this.  Also, fixing up the TPM entry in the device tree.
Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-11-29 06:54:24 +00:00
Srinivas Hegde 2d589cfc6c arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
We seem to be passing CPPFLAGS to linker in x86 arch
ramstage. This is superflous as these are only meant
to be compiler flags and should not be passed to the
linker.

Change-Id: Ia3cd51be6be252aa796191cf0d2cd91d393c8878
Signed-off-by: Srinivas Hegde <srinivashegde@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-29 00:33:13 +00:00
Karthikeyan Ramasubramanian 892711fd77 soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM config
Select PSP_VERSTAGE_MAP_ENTIRE_SPIROM in Cezanne Kconfig instead of
common Kconfig.

BUG=None
TEST=Build BIOS image and boot to OS in dewatt.

Change-Id: I476971700824fed06d17000001afc075105fa1ee
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79306
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-28 16:49:09 +00:00
Karthikeyan Ramasubramanian b6ab7baa38 soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
Earlier entire SPI ROM was mapped to memory. With limited TLB resources
in PSP, this approach hit the limit on systems using 32 MiB SPI ROM.
Therefore regions in SPI ROM were mapped on need basis. This works well
on Picasso, Mendocino and Phoenix SoCs. But unfortunately this causes
boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM
and enable it in Cezanne SoC. For other SoCs, keep the configuration
disabled so that only the required SPI ROM region is mapped.

BUG=b:309690716
TEST=Build and boot to OS in both Dewatt and Skyrim.

Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-11-28 16:48:49 +00:00
Matt DeVillier 132b5a4262 Update amd_blobs submodule to upstream main branch
Updating from commit id e4519efca746 (2023-11-15):
  Revert "picasso: Update PSP binaries to release 0.8.13.7B"

to commit id 68ebd4b567f4 (2023-11-27):
  PCO: Update ABL to version CABLRV21080200

This brings in 1 new commit:
68ebd4b567 PCO: Update ABL to version CABLRV21080200

Change-Id: I4cf528c2d2489782758d2e16ea9201324c466919
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-28 16:15:13 +00:00
Martin Roth 50a3d6fcd8 soc/amd/genoa: Add openSIL to Genoa Kconfig
Select opensil & opensil_genoa. This enables openSIL for Genoa, allowing
the build to be tested.

Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-28 13:17:53 +00:00
Arthur Heymans 791ce58e6e vendorcode/amd: Hook up opensil
OpenSIL has a native buildsystem using meson and configuration mechanism
using kconfiglib.

To be able to use the coreboot toolchain with opensil, meson crossfiles
are used, which get generated by coreboot makefiles.

Configuration of opensil is done in a similar fashion with a template
defconfig after which kconfiglib is called to generate headers.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide2d181914116119dfd37b1511d89ea965729141
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76511
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-28 13:17:13 +00:00
Naresh Solanki 1d6eeff171 acpi: Enable 64bit ECAM resource
Adjust ACPI DSDT to support ECAM resource above 4GB by modifying the PCI
ECAM Resource Consumption settings. The changes include specifying a
QWordMemory resource template, accommodating non-cacheable, read-write
attributes, and adjusting the address range.

Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-27 21:10:41 +00:00
Leo Chou 16875ec8e3 mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory parts
Add taeko new supported memory parts in mem_parts_used.txt, generate
spd-3.hex for these parts.

1. Samsung       K4UBE3D4AB-MGCL
2. Micron        MT53E1G32D2NP-046 WT:B

BUG=b:312363368
TEST=Use part_id_gen to generate related settings

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
2023-11-27 14:48:20 +00:00
Keith Hui b4a8937045 mb/asus/p8z77-m_pro: Drop useless early init code
Drop code that puts Super I/O into config mode, select serial device,
then leave config mode right away having done nothing.

I'll also take this chance to revise its #includes based on
include-what-you-use results.

Change-Id: I304fc1610740375b59121b6b8784122440795838
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73693
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27 14:41:29 +00:00
Keith Hui 5cf4628f4f mb/asus/p8z77-m: Properly configure early serial
Board was not producing serial output until well into ramstage.

To fix, select SUPERIO_NUVOTON_COMMON_COM_A Kconfig to tell
nuvoton_enable_serial() to route serial port A signals to the outside,
not GPIO8x.

TEST=Full native raminit debug log received over serial by minicom.

Change-Id: I376a79dd76ffa5f4d47e7c0cb53680e173e1ad78
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-27 14:39:23 +00:00
Kapil Porwal 642b789e70 mb/google/rex/var/screebo: Enable BT audio offload config
Enable BT audio offload of ALC1019_ALC5682I_I2S based on fw_config.

BUG=b:299510759
TEST=Build and boot to Screebo. Verify the config from serial logs.

w/o this CL -
```
[SPEW ]  ------------------ CNVi Config ------------------
[SPEW ]  CNVi Mode        = 1
[SPEW ]  Wi-Fi Core       = 1
[SPEW ]  BT Core          = 1
[SPEW ]  BT Audio Offload = 0
[SPEW ]  BT Interface     = 1
```

w/ this CL -
```
[SPEW ]  ------------------ CNVi Config ------------------
[SPEW ]  CNVi Mode        = 1
[SPEW ]  Wi-Fi Core       = 1
[SPEW ]  BT Core          = 1
[SPEW ]  BT Audio Offload = 1
[SPEW ]  BT Interface     = 1
```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I6c713752f3f0bf58b5ebd78b904e773fdbf16e06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77755
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27 12:57:47 +00:00
Tyler Wang 64c9520b0c mb/google/nissa/var/craask: Enable PIXA touchpad
Add PIXA touchpad for variants of craask.

BUG=b:310489697
TEST=build craask firmware and test with PIXA touchpad

Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27 02:15:44 +00:00
Patrick Georgi 41419d9c30 util/kconfig: Import some more of Linux's build infra
cmd and cmd_conf_cfg are necessary for `make menuconfig`
and `make nconfig`.

Change-Id: Ie16ef31a8e0137f3fd4129fb73ca6ef4669173cc
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79264
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-27 00:02:09 +00:00
Felix Singer 0b82a2e370 doc/releases/4.22: Replace unicode chars with ASCII
Change-Id: I0b8419a8ad01d711362733e02ace89c48d2893b2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-11-26 23:46:18 +00:00
Patrick Georgi 786292a0fc libpayload/unit-tests: Rename ARCH_BIG_ENDIAN to ARCH_MOCK_BIG_ENDIAN
This fixes commit 12ae850dfc which used the wrong symbol, and previous
versions of Kconfig didn't notice.

Change-Id: I7145fd81a30a1455a6dd2c7f24564956a116d180
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79263
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-25 16:00:19 +00:00
Patrick Georgi 0eab62b9cf util/kconfig: Uprev to Linux 6.6's kconfig
Upstream reimplemented KCONFIG_STRICT, just calling it KCONFIG_WERROR.
Therefore, adapt our build system and documentation. Upstream is less
strict at this time, but there's a proposed patch that got imported.

TEST=`util/abuild/abuild -C` output (config.h and
config.build) remains the same. Also, the failure type fixed in
https://review.coreboot.org/c/coreboot/+/11272 can be detected,
which I tested by manually breaking our Kconfig in a similar way.

Change-Id: I322fb08a2f7308b93cff71a5dd4136f1a998773b
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 14:51:41 +00:00
Patrick Georgi 47282a90de tree wide: Rename VBOOT_MEASURED_BOOT* to TPM_MEASURED_BOOT
This follows commit c79e96b4eb which did the rename across the tree
except in these places. Remove the flag from CHROMEOS abuild builds
because it never really belonged there.

Change-Id: If98fa27f64d6b676d3edf68ba6fbaacf7ac422e4
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79258
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:55:22 +00:00
Patrick Georgi b6954fa16f configs: Drop reference to USE_CANNONLAKE_FSP_CAR
This follows commit 5e8c906 which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

As the config file's name indicates that its sole purpose is to test
integration of FSP's CAR, just drop the configuration altogether.

Change-Id: Idde7bf590c935a83e8f85f7d0a8e4b6954702319
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-25 13:55:09 +00:00
Patrick Georgi 37626f2aae configs: Rename UART_DEBUG to INTEL_LPSS_UART_FOR_CONSOLE
This follows commit a96e66a76f which did the rename across the tree
except here. Since Kconfig is going to become more strict about unknown
symbols, fix it.

Change-Id: I3b855085d4be13622e8f38ff651d576e719b682c
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79256
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:55:01 +00:00
Patrick Georgi b667ce6382 configs: Drop references to MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
This follows commit 6615c6eaf7 which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

Change-Id: I7b7f2e4c0774919a55083f7c5348f2b5031c8287
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:54:52 +00:00
Patrick Georgi bbaa1f00f3 configs: Drop references to CPU_QEMU_X86_SMMLOADERV2
This follows commit 88407bcd which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

Change-Id: I19d26de8003c51437ea62e04083a14c3587a4665
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79254
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-25 13:54:43 +00:00
Patrick Georgi 6619afac04 configs: Drop references to CPU_QEMU_X86_PARALLEL_MP
This follows commit e2d291b5 which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

Change-Id: I838f98d07fc0448dda6c02b58d7c5639992c77a2
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79253
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:54:34 +00:00
Patrick Georgi 06fb738497 configs: Rename PXE_SERIAL_CONSOLE to IPXE_SERIAL_CONSOLE
This follows commit 238ff1e9c which did the rename across the tree
except here. Since Kconfig is going to become more strict about unknown
symbols, fix it.

Change-Id: Ic31b8ae353ec07e8b8adab46b604365be4be44d9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-25 13:54:27 +00:00
Martin Roth c0461f4a51 Docs/releases: Finalize 4.22/4.22.01 release notes
Now that the 4.22 release tag has been added to git, update the release
notes with the final statistics and wording.

We also decided to add a fix submitted immediately after the 4.22
release was tagged into the release package and do a point release.

This also adds an expected date for the next release

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iae9653a275fcc1d11efbb88e12676f332be0a5dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79147
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-25 03:05:11 +00:00
Elyes Haouas 2731fa619b crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
Changelogs:
  * https://gcc.gnu.org/gcc-12/changes.html
  * https://gcc.gnu.org/gcc-13/changes.html

Porting guides:
  * https://gcc.gnu.org/gcc-12/porting_to.html
  * https://gcc.gnu.org/gcc-13/porting_to.html

Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 23:31:03 +00:00
Arthur Heymans 5ee1d23bcc soc/amd/genoa: Hook up microcode updating
Also update the regular expression to find the genoa blobs.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iba0109c049019a22cba1e0358cedbd9c198c6569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-24 17:01:10 +00:00
Patrick Georgi 0a48cfa3a5 util/kconfig: Uprev to Linux 6.5's kconfig
TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: If717d064d87b0045f276a4ee963db0a62230f5d8
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 16:50:27 +00:00
Patrick Georgi 34b149b508 util/kconfig: Uprev to Linux 6.4's kconfig
TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: Idbcd88165271b58ba3697c66df447af0b8b57b1b
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79181
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-24 16:50:18 +00:00
Patrick Georgi 54cec70650 util/kconfig: Uprev to Linux 6.3's kconfig
Minor bugfix, plus stuff that doesn't really affect us.

TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: I0af0c2ae4cb11bb58457830ffcd8bb8c2422a3d1
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79180
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-24 16:50:09 +00:00
Patrick Georgi 7eab8ef8b7 util/kconfig: Uprev to Linux 6.2's kconfig
The upstream build system uses a newly introduced function `read-file`,
so copy that in from Linux 6.2.

TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: Ic100bf189ebd3eaa0eb26904ae8602910329a180
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 16:50:00 +00:00
Patrick Georgi 7f93aa4919 util/kconfig: Uprev to Linux 6.1's kconfig
This also cleans up our patch queue.

TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: I79159130ba3515ede59e9fb9fbf087e2ed76257a
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 16:49:51 +00:00
Scott Chao f47e85fc72 mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC
In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system
and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level
triggered and it causes AP (Application Processor) to keep sending
GET_NEXT_EVENT to EC during resume from suspend by connecting AC.

So we change GPP_F17 to edge triggered to avoid this condition.

BUG=b:308716748
TEST=Original failure rate was 7 out of 10 times and it reduced to
0 out of 60 times on six joxer systems.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-24 08:31:41 +00:00