Update passive temperature threshold value from 50C to 52C and
critical temperature threshold from 90C to 80C for TSR1 sensor.
BUG=b:79779737
TEST=Build and verified on Bobba/Bobba360/Sparky/Sparky360 boards
Change-Id: Iffef8afe0f1c6c80a6ae8ecb831aaf749443980e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the configuration of EC_SYNC IRQ to be level
triggered to match the EC behavior.
Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Change tcc offset from 0 to 10 for fleex.
Refer to b:117789732#1
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use GPIO_134 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BRANCH=none
BUG=crbug:896347, b:118443377
CQ-DEPEND=CL:1298699
TEST=verify sensor events coming in on a reworked board
with companion EC and kernel patches
Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/29278
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Update PSV values for cpu and sensers.
2. Change PL1 min value from 3w to 4.5w.
3. Change TSR2 TRT source from charger to CPU.
Refer to 112448519#comment31.
BUG=b:112448519
TEST=Build coreboot for Octopus board
Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of
part_num_store that holds the number of DRAM part. It ensures that
host advertises the supported size to read part number from the EC.
BUG=b:115697578
Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This change uses the newly added macros for configuring the same GPI
pad(GPIO_135) for IRQ (normal interrupt operations) and
wake (interrupt for waking from S3/S0ix) for the trackpad device. The
other pad GPIO_142 is now configured as not connected.
BUG=b:117553222
TEST=Verified that yorp and bobba wake from S3 and S0ix using
trackpad.
Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change udpates FMAP to wrap MRC training data in RW_PRESERVE
section so that we don't lose the data when performing full firmware
updates on octopus.
BUG=b:117882029
TEST=Verified that chromeos-firmwareupdate doing full firmware update
preserves training data on octopus.
Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.
BUG=b:117298114
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz
Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Need to tune I2C bus 0 clock frequency under the 400KHz
since this bus attached the Stylus EMR pen and need meet the spec.
Bug=b:117297214
TEST=flash coreboot to the DUT and measure I2C bus 0 clock
frequency whether under 400KHz
Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 3 for DVT.
BUG=b:115697578
TEST=verified it in Bobba EVT board which rework ram id.
Change-Id: I0fb457d8772f5038e5d90188d7682956ddfad46b
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All ampton boards should have the DRAM info configured in CBI and so
DRAM_PART_NUM_ALWAYS_IN_CBI is already selected for ampton. This
change gets rid of the redundant minimum board id value for Ampton.
BUG=b:117071184
Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fleex does not have any device on I2C0 and hence this change disables
I2C0 device (16.0) in devicetree and gets rid of the I2C tuning
parameters for I2C0.
BUG=b:115600671
Change-Id: Ib799eae05b667cee2272bbd37f0ca44b7cec66cd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Need to tune I2C bus 0/6/7 clock frequency under the 400KHz for
digitizer, touchpad, and touchscreen.
Bug=b:117126484
TEST=flash coreboot to the DUT and measure I2C bus 0/6/7 clock
frequency whether can <400KHz
Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28907
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT.
BUG=b:116721822
TEST=Verified it in Fleex EVT board which rework ram id.
Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Need to tune I2C bus 6 clock frequency under the 400K Hz
Bug=b:115600671
TEST=flash coreboot to the DUT and measure I2C bus 6 clock
frequency whether arrive to 398.07K Hz
Change-Id: I5cc1f67f0db0553cb8424f81408ed4686cddb2fb
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Need to tune I2C bus 6 clock frequency under the 400KHz
Bug=b:116543001
TEST=flash coreboot to the DUT and measure I2C bus 6 clock
frequency whether arrive to 399.1KHz
Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since I2C bus 7 attached the touchscreen device however Phaser units
that haven't it. So for avoiding side effects, we need close I2C bus
7 SCL and SDA respectively.
BUG=none
TEST=according to sku_id (Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3)
distinguish whether close these gpios.
Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28669
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jett Rink <jettrink@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit creates an ampton variant for Octopus. The initial settings
are copied from Bip, but the following changes are made to support
hardware differences:
* GPIO_66 is not connected (LTE).
* GPIO_67 is not connected (LTE).
* Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet.
* GPIO_143 is not connected.
* GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected.
* EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146.
* GPIO_213 is not connected.
* GPIO_214 is not connected.
BUG=b:111498206
TEST=None
Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update Power Limit1 and Power Limit2 values along with stepsize.
Correct the charger effect for Temperature sensor2.
BUG=b:112448519
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT.
BUG=b:115965629
TEST=verified it in meep proto board which rework ram id.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363
Reviewed-on: https://review.coreboot.org/28658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The board version is part of EC's EEPROM, but is not being populated
from EEPROM. Instead a default Kconfig parameter is returned as board
version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable
requesting the EC for board version.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This modification for DVT build and use CBI method
enable all memory particles.
BUG=b:112870780
TEST=verify it under the EVT unit and pre-test EVT
unit(rework RAM ID follow the proposal) respectively.
Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.
TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.
Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also removed internal pull ups for CX_PREQ_L and
CX_PREQ_L signals as they have external pull ups.
BUG=b:110654510
TEST=On Yorp Proto 2, flashed image and verified that it boots to OS.
Checked Wake-on-Wifi works with both cnvi and pcie modules.
Also executed a few suspend resume cycles.
Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/28328
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update TSR1 trip point from 48C to 50C.
Also, change power limit2 minimum value from 8W to 10W.
These are the values as per recent thermal tuning.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28187
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates GPIO configuration for bobba boards with id >= 1
This follows the same model as fleex:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
BUG=b:112354568
TEST=Built firmware for bobba
Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28071
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=none
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: Ic61a69e19e97520da0702dfe6cb7496563fc34f4
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Follow thermal table (b:112274477 comment#1) for first tunning.
BUG=b:112274477
TEST=Match the result from DPTF UI.
Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:112288077
TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry.
Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PERST signal is asserted/deasserted by ACPI routines during
suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in
failure to resume from suspend state with wake-over-WLAN. This change
removes the IOStandby configuration for WLAN_PE_RST.
BUG=b:112371978
Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When CNVi is being used, external wake using GPIO_119 is not
required. This change configures GPIO_119 as PAD_NC if CNVi is taken
out of reset.
BUG=b:112371978
Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses drivers/intel/wifi chip for CNVi device to ensure
that:
1. Correct device name shows up in ACPI node
2. It is possible to pass any parameters from devicetree to wifi
driver for SSDT generation.
BUG=b:112371978
Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change checks to see if CNVi module is out of reset:
1. If yes, then PCIe device for WiFi is disabled.
2. If no, then CNVi device is disabled.
BUG=b:112371978
Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
