Commit Graph

45235 Commits

Author SHA1 Message Date
Felix Held 1105fe8913 soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_command
When wait_for_ready returned a timeout, execute_command still ended up
returning success. Fix this be returning a failure in this case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id012e74e26065c12d003793322dcdd448df758b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15 22:38:31 +00:00
Felix Held a3930dafd4 soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state
Introduce and use enum spi_dump_state_phase to indicate from which phase
of the SPI transfer dump_state gets called to print the relevant debug
information for that phase.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15 22:38:04 +00:00
Felix Held 6b0f45199c soc/amd/common/include/spi: add Cezanne-specific comment
The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined
compared to the previous generations. It is unclear if adding some
special handling for Cezanne would be worth the effort, since the
current code just doesn't use the last byte which should be safe to do,
since this only affects the maximum number of bytes that can be used for
one SPI transaction. Having another byte to use on Cezanne wouldn't
reduce the number of SPI transactions to write a 256 byte data block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15 22:37:50 +00:00
Felix Held 601a971545 soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of
the SPI controller's MMIO region for Stoneyridge and Picasso. Both
SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended
up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH
isn't changed.

TEST=Timeless build results in identical image for Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15 22:37:42 +00:00
Jakub Czapiga 19ad39b7f2 tests/lib/lzma-test: Fix uninitialized array error
Change-Id: I5b10eef3dd82068f97d4d875f3da813a5aca07a7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60112
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15 17:07:27 +00:00
Rob Barnes a1430c340e mb/google/guybrush: Set TPM to to be kernel power managed.
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause
the TPM kernel driver to send a shutdown command before s0i3 entry. This
change depends on S0i3 verstage running and reinitializing the TPM.

BUG=b:200578885
BRANCH=None
TEST=TPM shutdown sent during s0i3 entry on guybrush

Change-Id: I206022cc2a29690186206966c5d45bd55c303248
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15 17:07:14 +00:00
Dtrain Hsu 540951e374 mb/google/dedede/var/madoo: Generate new SPD ID for new memory parts
Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Micron MT53E512M32D1NP-046 WT:B
2. Samsung K4U6E3S4AB-MGCL
3. Hynix H54G46CYRBX267

BUG=b:209889645
BRANCH=dedede
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15 17:06:58 +00:00
Angel Pons bc62891378 Denverton-NS boards: Drop useless `thermal.asl`
The code in these files is meaningless, and can be dropped.

Change-Id: I11571885059e8d5f930f741172c74b25faa09a15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-15 15:55:49 +00:00
Casper Chang 0ccb7b2d48 mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8

BUG=b:204844399
TEST=USE="project_primus emerge-brya coreboot" and verified
     the setting meets the audible noise specification

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15 15:55:31 +00:00
Sean Rhodes 1b66bbaf83 mainboard/starlabs/labtop: Hook up Thunderbolt to CMOS
Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`.
Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-15 15:55:09 +00:00
Kevin Chiu 5e59f169ec mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM table
add Hynix H54G56CYRBX247 support

BUG=b:210365851
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     power on successfully

Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15 15:54:30 +00:00
Joey Peng cddded2f58 mb/google/brya/var/taniks: Configure DRIVER_TPM_I2C_BUS
Add I2C bus for taniks in Kconfig

BUG=b:210390520
TEST=emerge-brya coreboot and can boot to OS.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I9b1719c3140c13f67e7cb0e6a69257774884bd4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15 15:54:16 +00:00
Joey Peng 44633997d8 mb/google/brya/variant/taniks: Add memory settings
Based on the Taniks's schematic, generate memory settings.
Schematic version is G570_MB_CHROME_1207_1630_ADC.

BUG=b:209531192,b:209553289
TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0c0794fb94d1f6271de604835ae1d2b20696ee70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15 15:53:53 +00:00
Joey Peng 88efeafa66 mb/google/brya/variants/taniks: Configure GPIOs according to schematics
Add initial gpio configuration for taniks according to schematics
G570_MB_CHROME_1207_1630_ADC. The schematics reserved HPS and FP but
taniks doesn't use them, so set FP and HPS related pins to NC.

BUG=b:209492408, b:209553289
TEST=FW_NAME=taniks emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15 15:53:33 +00:00
Kyösti Mälkki 3990da0bfe soc/intel/denverton_ns: Fix MRC_RW_CACHE
It is required to set WPD (Write Protect Disable) bit
to make it possible to use MRC_RW_CACHE region with
CACHE_MRC_SETTINGS=y.

Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15 12:11:04 +00:00
Kyösti Mälkki fd13fb54ac soc/intel/denverton_ns: Use common SMBus support code
Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15 12:10:22 +00:00
Dmitry Ponamorev ccc27d2cca soc/intel/baytrail,denverton_ns: Call setup_lapic()
A custom board with soc/intel/denverton_ns does not respond to
the keyboard and does not boot from the sata/USB disks.
Last post code 0x7b and the last line that is displayed at log
from SeaBIOS is:
   All threads complete.

The issue is gone when adding setup_lapic() call to configure
EXTINT delivery of i8259 originated interrupts for the LAPIC.
Replicate call from other soc/ and make the call for both BSP
and AP CPUs.

Similar change was done for soc/intel/braswell in
commit b4f57bb3ca.

Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15 12:10:02 +00:00
Rex-BC Chen add2e93050 mb/google/corsola: move USB3 HUB reset funtion to bootblock
To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak
resistor, so we have to reset the hub as early as possible.
Otherwise the USB3 hub may be not usable. Therefore, move USB3 HUB
reset function to bootblock.

BUG=b:210065282
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60088
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15 07:52:34 +00:00
Julius Werner 0fd072d3f2 cbfstool: Clean up remnants of locate action
`cbfstool locate` and the associated -T switch were removed a looong
time ago (2015 in CB:11671). However, getopt and the help text weren't
cleaned up correctly. Fix that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib098278d68df65d348528fbfd2496b5737ca6246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-14 21:45:32 +00:00
Julius Werner 772714d3b3 cbfstool: Use converted buffer size for do_cbfs_locate()
The whole point of moving do_cbfs_locate() later (CB:59877) was that it
could use the file size that is actually going to be inserted into CBFS,
rather than the on-disk file size. Unfortunately, after all that work I
forgot to actually make it do that. This patch fixes that.

Since there is no more use case for do_cbfs_locate() having to figure
out the file size on its own, and that generally seems to be a bad idea
(as the original issue shows), also remove that part of it completely
and make the data_size parameter mandatory.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1af35e8e388f78aae3593c029afcfb4e510d2b8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-14 21:45:27 +00:00
Felix Singer 58ea2819ba mb/google/glados: Restore alphabetical order on Kconfig selects
Change-Id: I736234b9a960c58193fcf7bc9184c9581c6c953b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-14 19:56:40 +00:00
Rex-BC Chen ee56998a37 mb/google/corsola: set up open-drain ChromeOS pins
Set open-drain GPIOs for ChromeOS as input and high-z mode.
After applying this patch, we can measure these pins from 1.0V to
correct voltage (1.8V) to prevent wrong judgement of low/high.

Reference document:
MT8186_SoC_Pinmux_V1_1

BUG=b:209342636
TEST=measure pins voltage 1.8V on kingler board

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-14 17:06:24 +00:00
Rex-BC Chen ac6070a79f soc/mediatek/mt8186: add tracker dump
Tracker is a debugging tool, and MT8186 only supports AP tracker.
When bus timeout occurs, the system reboots and latches some values
which could be used for debugging.

This function will be triggered only when it encounters the bug
hanging issue.

BUG=b:202871018
TEST=range of registers are dumped as expected.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-14 17:06:12 +00:00
Zheng Bao da83d2c97f amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses "binary relative"
offsets and not "x86 physical MMIO address" like gen1.

The field additional_info in table header can tell if the absolute or
relative address is used.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

The related change in psp_verstage has been uploaded.
https://review.coreboot.org/c/coreboot/+/58316

The relative mode is the mode 1 of four address modes. The absolute
mode is the mode 0. Later we will implement mode 2. Not sure if mode 3
is needed.

It needs to be simple to work with psp_verstage change to make SOC
Cezanne work quickly. This patch is defacto a subset of
    https://review.coreboot.org/c/coreboot/+/59308
which implements the framework of address mode and covers mode
0,1,2. Some hardcode value like 29 can be removed in 59308.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-14 16:15:52 +00:00
Bill XIE d85cee8310 payloads/U-Boot: Fix various build errors
1. Fix the inconsistence of the target path of U-Boot payload
   between Kconfig and Makefile.inc.

2. Perform full clone (to the destined commit) in order to get
   tags.

3. Move stable commit id of U-Boot payload from Makefile to
   Kconfig, and make prompt consistent with it.

Change-Id: Ic0f11c16274456a452a0422e19fab0c61d8b5d5b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-14 16:13:06 +00:00
Rex-BC Chen 2efb6142ca soc/mediatek: add support for tracker version one
There are two versions for tracker system:
Version 1 for MT8186, and version 2 for MT8192 and MT8195.

Reference document:
MT8169_bus_dbg_tracker_cfg_reg.xls from MediaTek internal.

BUG=b:202871018
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59989
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-14 16:11:28 +00:00
Rob Barnes 3437a6fbb0 soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will
be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this
in PSP.

BUG=b:200578885, b:202397678
BRANCH=None
TEST=Verstage runs during s0i3 resume on Nipperkin

Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-14 16:03:40 +00:00
Sean Rhodes 941239d54d Documentation/releases: Update 4.16 release notes
* Add StarBook Mk V as new mainboard
* Add option to disable Intel Management Engine via HECI

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9675a6a8960d93ae6de285d8b25ffc48a763483e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13 23:47:23 +00:00
Elyes HAOUAS f79f775eda arch/x86/c_start.S: Remove duplicated "the" in comments
Change-Id: Ib1be1db6f475ad0e1f34703bfe1257d02b86742c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-13 23:46:54 +00:00
ravindr1 123312d6a5 soc/intel/common/cse: Update help text for CSE_OEMP_FILE
The OEM may create and sign an Audio component to extend the Audio
capability provided by Intel. The manifest is then signed, and the
signature and public key are entered into the header of the manifest
to create the final signed component binary. This creates a secure
verification mechanism where firmware verifies that the OEM Key
Manifest was signed with a key owned by a trusted owner. Once OEM KM
is authenticated, each public key hash stored within the OEM KM is
able to authenticate the corresponding FW binary.

Link to the Document:
https://www.intel.com/content/www/us/en/secure/design/confidential/software-kits/kit-details.html?kitId=689893
ADL_Signing_and_Manifesting_User_Guide.pdf

BUG=b:207820413
TEST:none

Signed-off-by: ravindr1 <ravindra@intel.com>
Change-Id: Id52b51ab1c910d70b7897eb31add8287b5b0166f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13 20:31:57 +00:00
Arthur Heymans 10f457af5f soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stack
Change-Id: I6b5864cfb9b013559cd318bc01733ba4d3792e65
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-13 17:52:04 +00:00
Julius Werner 25096eb950 cbfs: Enable CBFS verification Kconfigs
With the elimination of remaining non-verifying CBFS APIs in CB:59682,
CBFS verification is now ready to be used in its simplest form, so
enable the respective Kconfig options in menuconfig. Add a few more
restrictions to the TOCTOU_SAFETY option for problems that haven't been
solved yet, and transform a comment in cbfs.c into a die() to make sure
we don't accidentally forget implementing it once vboot integration gets
added.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifeba5c962c943856ab79bc6c4cb90a60c1de4a60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-12-13 14:14:39 +00:00
Julius Werner 20ad36547e cbfstool: Do host space address conversion earlier when adding files
In cbfs_add_component(), the |offset| variable confusingly jumps back
and forth between host address space and flash address space in some
cases. This patch tries to clean that logic up a bit by converting it
to flash address space very early in the function, and then keeping it
that way afterwards. convert() implementations that need the host
address space value should store it in a different variable to reduce
the risk of confusion. This should also fix a tiny issue where
--gen-attribute might have previously encoded the base address as given
in CBFS -- it probably makes more sense to always have it store a
consistent format (i.e. always flash address).

Also revert the unnecessary check for --base-address in
add_topswap_bootblock() that was added in CB:59877. On closer
inspection, the function actually doesn't use the passed in *offset at
all and uses it purely as an out-parameter. So while our current
Makefile does pass --base-address when adding the bootblock, it actually
has no effect and is redundant for the topswap case.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-13 14:11:53 +00:00
Wisley Chen 282957232e mb/google/dedede/var/lantis: Add fw_config probe for ALC5682-VD/ALC5682-VS
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:206676530
TEST=build

Change-Id: Ie73dc376078c0836edd980e09629399c5cc19594
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-13 14:03:33 +00:00
Kenneth Chan 38afe9e31c mb/google/guybrush/var/dewatt: Add Elan touchscreen
Add Elan 6918 touchscreen for dewatt. (EKTH6918 Product Spec V0.5)

BUG=b:208373433
TEST=emerge-guybrush coreboot chromeos-bootimage. Teseted with Elan 6918 touchscreen.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13 14:03:04 +00:00
Kenneth Chan d76d2e275f mb/google/guybrush/var/dewatt: Add Synaptics touchpad
Add Synaptics S9831 touchpad for dewatt.

BUG=b:208182457
TEST=emerge-guybrush coreboot chromeos-bootimage. Tested with Synaptics S9831 touchpad.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Id3e0636dd0ce5b80c2044c1dfca20ca7eac87fc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13 14:02:52 +00:00
Frans Hendriks 7e7ea2bdf0 MAINTAINERS: Replace maintainer for facebook, portwell and eltan
Change-Id: I3a6ecff4cf0c22e941261b77deefb272c1137a8e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13 14:02:17 +00:00
Paul Huang 0f0edeed2e mb/google/octopus: add ALC5682I-VS to be supported in the SSFC
Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different
hid name depending on SSFC.

BUG=b:198722640
BRANCH=octopus
TEST=Set CBI SSFC BIT9-11 to select codec, and test audio works

Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8
Signed-off-by: Paul Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2021-12-13 14:01:47 +00:00
Kane Chen c71e320bae mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:198689479
BRANCH=zork
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13 14:00:42 +00:00
Nico Huber aa709a4996 soc/amd/cezanne: Don't select CPU_INFO_V2 explicitly
It's already implied by PARALLEL_MP now.

Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-13 14:00:15 +00:00
MAULIK V VAGHELA f0a03b374a soc/intel/alderlake: Implement function to map physical port to EC port
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.

To correct this, coreboot has implemented function which converts
coreboot physical port mapping to EC's abstract port mapping.

Each SoC needs to implement this weak function since only SoC will have
correct physical port mapping data. This function should resolve issue
of port mismatch since coreboot will count only enabled ports and
provide correct EC port number in return.

BUG=b:207057940
BRANCH=None
TEST=Check if retimer update works on Redrix and correct port
information is passed to EC.

Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13 13:58:05 +00:00
MAULIK V VAGHELA a70288d9fc drivers/intel/usb4/retimer: Add function to correct EC port mapping
Currently coreboot interprets TCSS port number as per physical port
number while EC abstracts port number and provides indices as port
number. For example, if TCSS port 1 and 3 are enabled on the board,
coreboot will interpret port numbers as 0 and 2, but since only 2 ports
are enabled in the system EC will assign port numbers as 0 and 1.

This creates a port number mismatch while communicating between EC and
coreboot. This patch addresses issue where SoC can implement function
to map correct EC port as per port enabled in mainboard.

BUG=b:207057940
BRANCH=None
TEST=Check if code compiles successfully. Functionality will work once
function is implemented in SoC code.

Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13 13:57:39 +00:00
Tim Wawrzynczak 32f883e532 soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
For additional power savings during RTD3, the PMC can power-gate the
ModPHY lanes that are used by the PCH PCIe root ports. Therefore,
using the previous PCIe RP-type detection functions, implement ModPHY
PG support for the PCH PCIe RPs.

This involves:
1) Adding a mutex so only one power resource accesses the PMC registers
   at a time
2) OperationRegions to access the PMC's PG registers
3) Adding ModPHY PG enable sequence to _OFF
4) Adding ModPHY PG disable sequence to _ON

BUG=b:197983574
TEST=50 S0ix suspend/resume cycles on brya0

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59855
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13 13:56:01 +00:00
Tim Wawrzynczak b0d3a01941 soc/intel/alderlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-13 13:55:50 +00:00
Tim Wawrzynczak 1ac0dc164d soc/intel/tigerlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Tiger Lake.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-13 13:54:52 +00:00
Sugnan Prabhu S dcf045918b drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info
Add entry in ACPI table under IPU device to provide silicon type
information to IPU driver. IPU kernel driver can decide the type of
firmware to load based on this information.

BUG=b:207721978
BRANCH=none
TEST=Check for the ACPI entry in the SSDT after booting to kernel

Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f
Cq-Depend: chromium:3319905
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13 13:54:21 +00:00
Patrick Rudolph feab8bb195 src/arch/x86/exit_car: Fix regression on x86_64
The commit d023909b "treewide: Disable R_AMD64_32S relocation support"
clflush the address stored in _cbmem_top_ptr, which is the same address
cbmem_top() returns, instead of clflush _cbmem_top_ptr itself.

Fix that by providing the correct address to clflush.

Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13 13:52:25 +00:00
Felix Singer b32599ea89 soc/intel/cannonlake: Configure common FSP memory settings only once
`meminit_memcfg()` does common memory configuration, which is not
specific to each DIMM. Thus, move it out of the for-loop and call it
once.

Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13 12:56:04 +00:00
Ronak Kanabar ae0ea32c52 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02
The headers added are generated as per FSP v2471_02.
Previous FSP version was v2422_01.
Changes Include:
- UPDs description update in FspsUpd.h
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h

BUG=b:208336249
BRANCH=None
TEST=Build and boot brya

Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-12-13 06:09:15 +00:00
Jianjun Wang 8bb59ca2fa lib: Add __fls() (Find Last Set)
Implement __fls() as an alias for log2(), and remove the duplicate
definitions in commonlib/storage/sdhci.c.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-13 02:57:07 +00:00