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51084 Commits

Author SHA1 Message Date
Matt DeVillier 52c553e838 sb/intel/lynxpoint: Add Kconfig option to hide Intel ME 
On lynxpoint devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.

Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2022-12-23 14:20:39 +00:00
Subrata Banik 42f704a967 soc/intel/meteorlake: Add DPTF ACPI Device IDs into header file 
This patch adds DPTF ACPI Device IDs into the header file
(soc/dptf.h).

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib78258ac1b9a5252bb5e6fae4d7cc30a3f103e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71126
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 13:01:03 +00:00
Subrata Banik e9ac9f97e8 soc/intel: Drop SoC specific DPTF implementation 
This patch drops the SoC specific implementation as DPTF driver can
now fillin those platform specific data using SoC specific macros.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If65976f15374ba2410b537b1646ce466ba02969b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-23 13:00:30 +00:00
Subrata Banik af20628a48 drivers/intel/dptf: Implement API to fill DPTF platform info 
This patch fills in a generic platform info structure based on the
inputs from the SoC dptf header file (soc/dptf.h).

It will help to make things common and drop unnecessary back and
forth call between common code and SoC code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3521882495485cef686655abd65337515bae5faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71111
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 12:55:59 +00:00
Yidi Lin 63d26b82a3 soc/mediatek: Add DEVAPC_DEBUG option 
Add DEVAPC_DEBUG option and set this option to disabled by default.
This option prevents DEVAPC log flooding during the boot process. Enable
this option when we need to debug DEVAPC issues.

TEST=DEVAPC log is disabled by default.

Change-Id: I26bc0378b8a766c6a8cc4903d64a921c3e96b93f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 12:55:22 +00:00
Liju-Clr Chen aa9bb44504 mb/google/geralt: Pass SD card detect GPIO to payloads 
1. Add an option for SD card initialization.
2. If CONFIG SDCARD_INIT is configured, pass SD card detect GPIO to
   payloads for SD card detection and initialize MSDC for SD card
   configuration.

BUG=b:244250437
TEST=build pass

Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I2d3683eb673f438c9190c11d4679a3ca97c76a98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71136
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-12-23 12:54:42 +00:00
Felix Singer d252776668 tree: Replace And(a,b) with ASL 2.0 syntax 
Replace `And (a, b)` with `a & b`.

Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 10:18:55 +00:00
Felix Singer 35e65a8bc3 tree: Replace And(a,b,c) with ASL 2.0 syntax 
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where
possible.

Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 10:18:48 +00:00
Felix Singer 86bc2e708d tree: Replace Or(a,b,c) with ASL 2.0 syntax 
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where
possible.

Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 10:17:34 +00:00
Felix Singer 372573eaff tree: Replace ShiftLeft(a,b) with ASL 2.0 syntax 
Replace `ShiftLeft (a, b)` with `a << b`.

Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 08:30:39 +00:00
Felix Singer 3c9291b335 tree: Replace ShiftLeft(a,b,c) with ASL 2.0 syntax 
Replace `ShiftLeft (a, b, c)` with `c = a << b`.

Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 08:30:09 +00:00
Felix Singer 034920c1d4 tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntax 
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was
simplified to just `a >> b`.

Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-23 03:16:35 +00:00
Kyösti Mälkki 100f92c54f mb,x86/smm: Disable unused IO traps 
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented
the IO trap handler.

Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 03:09:20 +00:00
Martin Roth 4c61294498 Docs: Add page for external resources 
This is a page to add links to other sites that have firmware related
material, or other things that are of interest to the community.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icf411e67bf865426b1a3b99ecbabed2302a7b738
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
 2022-12-23 02:54:48 +00:00
Matt DeVillier 3d352a7218 mb/google/poppy/nocturne: Fix touchscreen reset GPIO config 
The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an
internal pull-down, which puts it in a state of contention when the
reset pin is released / set to high. Fix this by changing the reset
GPIO to PAD_CFG_GPO like all other poppy variants use for the
touchscreen reset.

TEST=build/boot nocturne, touchscreen still works.

Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 00:45:02 +00:00
Matt DeVillier 7f2c0bf838 mb/google/sarien: Add default fmap for non-ChromeOS builds 
Test: build/boot google/sarien with non-ChromeOS build, edk2 payload.
Linux 5.15, Windows 11 tested.

Change-Id: Ibc1857e6b120b0bb827ed610981c4d2bf8f78d1f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-23 00:35:54 +00:00
Matt DeVillier c5ec497bbc mb/google/hatch: Use runtime detection for touchscreens/digitizers 
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple hatch variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 00:22:40 +00:00
Matt DeVillier 251d443e8b mb/google/hatch: Set touchpad/screen IRQs to LEVEL vs EDGE 
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-23 00:22:03 +00:00
Matt DeVillier 4534ed7a62 mb/google/hatch/*: Add missing enable GPIO for ELAN touchscreens 
Some ELAN touchscreens were missing the entries for the enable GPIO
and associated delays. Add them to variants with ELAN0001 touchscreens
missing the entries.

TEST=tested with rest of patch train

Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-12-23 00:21:06 +00:00
Matt DeVillier 525c61f74e mb/google/hatch: Implement touchscreen power sequencing 
For touchscreens on hatch variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 00:19:06 +00:00
Matt DeVillier c0edb925e6 mb/google/hatch: Add method to set GPIOs in romstage 
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-23 00:15:45 +00:00
Matt DeVillier 63cde524b7 mb/google/poppy/rammus: disable USB xDCI 
With xDCI enabled, the right USB-C port does not work for USB data.
Additionally, it was disabled in stock ChromeOS firmware.

TEST=build/boot rammus, confirm right USB-C port works for booting,
under OS in Windows/Linux.

Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-23 00:14:56 +00:00
Matt DeVillier 2328144577 mb/google/zork: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on berknip/morphius, verify all
touchpad functions work correctly.

Change-Id: I9d8362719ddbfe523dd83964556b05bb8f1bb1ba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-23 00:12:53 +00:00
Matt DeVillier 74efac1a3f mb/google/volteer: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad
functions work correctly.

Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-23 00:11:22 +00:00
Sean Rhodes 823a329bb8 soc/intel/apollolake/acpi: Remove STOM from ACPI 
This should only contain resources that the PCI domain uses. Stolen
memory prevents the PCI domain from allocating anything where it is.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1562396f0b747a81bbc584314956809bd3865ff9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 21:17:57 +00:00
Sean Rhodes a17864c2c9 soc/intel/apollolake/acpi: Improve comments and unify code word spelling 
ACPI: Improve comments and unify code word spelling

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1efbe930d0b8daec7c7bd2c1d84a4a3a5cad2ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 21:17:40 +00:00
Sean Rhodes 8264122122 soc/intel/apollolake/acpi: Tidy the Legacy video RAM 
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie6572638c6bbe910745de55afa44458fb6b8db9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66240
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 21:17:33 +00:00
Sean Rhodes 197cfe03d5 soc/intel/apollolake/acpi: Tidy the PCI Memory Region 
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8997f9c111142a908b60675023d1a7dd86d3632a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66238
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 21:17:26 +00:00
Sean Rhodes de19bc372b soc/intel/apollolake/acpi: Add bits of TOLUD register 
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2022-12-22 21:17:16 +00:00
Sean Rhodes 759aa17e79 soc/intel/apollolake/acpi: Remove TOUUD as it is not used 
Remove Top of Upper Usable DRAM Low from MCHC as it isn't needed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifdd8c9ba61c5b1c6b154369413470e431ce8f5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 21:17:04 +00:00
Sean Rhodes a49cd32da0 soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONF 
The current implementation of the MCRS had several issues with BARs
and MMCONF not being available:

    [    0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb
    [    0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window
    [    0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit]
...
    [    0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.138300] PCI: not using MMCONFIG
    [    0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources
    [    0.149679] PCI: not using MMCONFIG
    [    0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.

This new MCRS, tested on the Star Lite Mk IV, resolves these issues:

    [    0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb
    [    0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit]
    ...
     [    0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.138460] PCI: not using MMCONFIG
    [    0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2022-12-22 21:16:13 +00:00
Matt DeVillier 6a803bfae6 mb/google/reef: update ACPI HID/CID for Synaptics touchpad 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on coral, verify all touchpad
functions work correctly.

Change-Id: I161eb953bf8bceb353cf43803ee948c522928892
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:44:51 +00:00
Matt DeVillier f75172fdcc mb/google/poppy: update ACPI HID/CID for Synaptics touchpad 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on nami, verify all touchpad
functions work correctly.

Change-Id: I0611da8bbea41565e603a1a1b7cc20226ba21c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:44:18 +00:00
Matt DeVillier 2793716910 mb/google/hatch: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on bobba, verify all touchpad
functions work correctly.

Change-Id: I4fd66be21eeff5f37b58a8922c49683a28685064
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:43:12 +00:00
Matt DeVillier f39e105deb mb/google/kahlee: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on liara, verify all touchpad
functions work correctly.

Change-Id: I89ca02629803882e7ed2048a5a26868fc2de41a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:42:33 +00:00
Matt DeVillier 148207a8b7 mb/google/hatch: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on akemi/kohaku, verify all touchpad
functions work correctly.

Change-Id: Icb552caa69428908e5e3342139b578a145fa2797
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:41:54 +00:00
Matt DeVillier 61c2446142 mb/google/guybrush: update ACPI HID/CID for Synaptics touchpad 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot ChromeOS, Linux 5.1x, Windows 10 on dewatt, verify all
touchpad functions work correctly.

Change-Id: I00efde6f007d57166cd82f76d2f389dedce57466
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:41:34 +00:00
Matt DeVillier 2f5aec4b50 mb/google/dedede: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on drawcia, verify all touchpad
functions work correctly.

Change-Id: I43eb5bc394a3fbfd4109f2e6c274ec66fc01d46d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:40:56 +00:00
Matt DeVillier e9f0ed5960 mb/google/brya: update ACPI HID/CID for Synaptics touchpads 
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=untested on brya, but tested under Windows/Linux on all other
boards in the tree using Synaptics touchpads.

Change-Id: Ia9351185b918f2d6f2d2be110b88e8310d37a03f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:40:17 +00:00
Matt DeVillier ba9f0c3817 mb/google/volteer: Add missing audio codec to HDA probe 
Audio codec RT1011_ALC5682I_I2S is listed as a fw_config option in the
baseboard, but missing from the HDA device probe list in the variant
overridetrees, preventing it from being detected at boot.

TEST=build/boot lindar, verify audio codec identified and HDA device not
disabled by fw_config.

Change-Id: Ib40b095688aac5cf4e0a60dcac250023c4f04c9f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:39:12 +00:00
Matt DeVillier a0e32aafee mb/google/reef: Use runtime detection for touchscreens 
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple reef variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I8c90074515b1c7d3ab742768d7bbd904fec256d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 20:38:05 +00:00
Matt DeVillier 48894ea620 mb/google/reef: Set touchpad/screen IRQs to LEVEL vs EDGE 
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I1000df10eea5670bf1bc8d04c736150b6a5e26a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:37:33 +00:00
Matt DeVillier beb58a93cf mb/google/reef: Implement touchscreen power sequencing 
For touchscreens on reef variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit). As the GPIOs are
already correct in ramstage, only the romstage ones need to be set.

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I10d1789c8de23653bac81e1f9604a47f93fa3f7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 20:36:42 +00:00
Matt DeVillier 40c8cc9cde mb/google/reef: Add method to set GPIOs in romstage 
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: Id3ab412183e5c5d534b2e1dea3222c729c25118b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 20:35:01 +00:00
Matt DeVillier 0d54a65819 mb/google/volteer: Use runtime detection for touchscreens 
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple volteer variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 20:34:03 +00:00
Matt DeVillier 0bffd0a1ae mb/google/volteer: Set touchscreen IRQs to LEVEL vs EDGE 
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 20:32:25 +00:00
Matt DeVillier 7ed6130428 mb/google/volteer: Implement touchscreen power sequencing 
For touchscreens on volteer variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 20:31:48 +00:00
Matt DeVillier 7413815a01 mb/google/volteer: Add method to set GPIOs in romstage 
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 20:27:21 +00:00
Sean Rhodes 1263622106 mb/starlabs/*: Bind console serial output to EDK2_DEBUG 
Configure the UART port but only enable UART debug for EDK2
debug builds.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-22 19:07:40 +00:00
Jonathan Zhang 8ab5e15aca inc/dev/pci_def.h: add definitions for RCEC EA Ext. Capbility 
Root Complex Event Collector Endpoint Association Extended
Capability is defined in section 7.9.10 of PCIe 5.0 spec.

Add its Extended Capability ID, association bitmap for RCiEPs
register, and RCEC associated bus numbers register.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7bede8ed88304a2925e6e1e4128bcdd625ee0e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-22 19:06:49 +00:00