Have the Skylake SOC generate ACPI timing values for the enabled I2C
controllers instead of passing it in the DSDT with static timings.
The timing values are generated from the controller clock speed and
are more accurate than the hardcoded values that were in the ASL which
were originally copied from Broadwell where the controller is running
at a different clock speed...
Additionally it is now possible for a board to override the values
using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then
the kernel will generate its own timing using the same forumla, but if
the SDA hold time value is zero the kernel will NOT generate a correct
value and the SDA hold time may be incorrect.
This was tested on the Chell platform to ensure all the I2C devices on
the board are still operational with these new timing values.
Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.
Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/15447
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add ACPI NHLT table generation that the current hardware
supports as well select the hardware used on the board.
Amenia has support for two audio codecs, Dialog for
headsets and Maxim for speakers.
Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15024
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The nvs.h header is the one which defines global_nvs_t proper.
Don't rely on an indirect inclusion.
Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15503
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Every other platform has global_nvs_t as a typedef. For some
reason apollolake didn't bother following current conventions.
Fix this omission to allow for better code sharing and consistency.
Change-Id: Id596eed517737759a64ce803c89ea2a05cbe2cce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15502
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
If read_vbnv finds that the vbnv_copy is not valid, it initializes it
with the correct HEADER_SIGNATURE and other attributes. However, the
vbnv copy is checked for validity and initialized at the vboot layer as
well. Since, vboot is the owner of this data, it should be the one
initializing it. Thus, if read_vbnv sees that the data is not valid,
simply reset it to all 0s and let vboot layer take care of it. This also
removes the need for additional checks to ensure that the dirty vbnv
copy is properly updated on storage.
Change-Id: I6101ac41f31f720a6e357c9c56e571d62e0f2f47
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch exposes a function to read pmc bar.
PMC bar is read in function read_pmc_mmio_bar which
is defined static in file pmutil.c. This patch exposes
that functionality to call it from other files.
BUG=chrome-os-partner:53438
TEST= Read the PMC bar value properly from outside
pmutil file.
Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If there is an external 16550 like UART, one needs to enable
the appropriate address ranges before console_init() is called
so that the init sequence can reach the external UART. Otherwise
the UART will only start working in ramstage and will produce
unreadable characters in romstage due to the lack of initialization.
Tested-on: Siemens MC_BDX1
Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15495
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add support for a fourth info block type to hwilib. This block
provides new values and is now variable in length.
Change-Id: Ia928b4a98b806ba3e80fb576b78f60bb8f2ea3fc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides()
functions should be able to be leveraged on all Intel SoCs
which support NHLT. Therefore provide that functionality and
make skylake use it.
Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The nhlt_soc_add_endpoint() is no longer used. Drop its declaration.
Change-Id: I3b68471650a43c5faae44bde523abca7ba250a34
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15489
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Utilize the new NHLT helper functions by driving the NHLT
endpoints through data descriptors.
Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15488
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to ease the porting of supporting NHLT endpoints
introduce a nhlt_endpoint_descriptor structure as well as
corresponding helper functions.
Change-Id: I68edaf681b4e60502f6ddbbd04de21d8aa072296
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Change PCI macros in such a way they can be transparently used across
romstage and ramstage.
Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15483
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- Add all, clean and distclean to .PHONY
- Rebuild nvramcui.elf when the makefile changes.
- Update libpayload target to $(LIBPAYLOAD_DIR) target - these are the
same thing, but by using the variable it makes it more obvious.
- Remove .config.old as well as .config when running distclean.
- Add CFLAGS to the LPGCC command line:
-- Enable all warnings, set warnings as errors.
-- Optimize for size
-- Enable '-ffreestanding -nostdinc -nostdlib' to keep from building in
system functions and to fix the warning:
libpayload.h: warning: conflicting types for built-in function 'log2'
static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; }
Change-Id: Icc6c70b259cd7c22dc960cdb732927f9c0c93ee8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14482
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
New UPDs added to header files as well as many comment fixes. Memory
infor is now defined in FspmUpd.h and added ability to skip CSE RBP
for coreboot. Removes some UPDs that are no longer available from
source.
BUG=chrome-os-partner:54677
BRANCH=none
TEST=built and tested with FSP 143_10 version
Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15459
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, read_vbnv performs a reset of the vbnv cache if it is not
valid. However, this information is not passed up to the vboot layer,
thus resulting in missed write-back of vbnv cache to storage if vboot
does not update the cache itself.
Update read_vbnv to return a value depending upon whether it wants a
write-back to be performed when save is called.
Return value:
0 = No write-back required
1 = Write-back of VBNV cache is required.
Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15457
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines.
Without this SDCARD will throw data read/write errors.
BUG=chrome-os-partner:54676
TEST=Build and boot to OS.
Verify SD card is detected and data read/write works well.
Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15345
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if set in NVS.
Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15026
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Configure unused Pads as NC
and sort the pads according to the gpio community.
Move the pad configurations from mainboard to gpio.h
BUG=none
TEST=Boot to OS and check all functionalities.
Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15327
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The different entry points (0x100, 0x140, ...), which were defined in
the RISC-V Privileged Specification 1.7, aren't used anymore. Instead
the Spike bootrom jumps at the start of our image, and traps are handled
through mtvec.
Change-Id: I865adec5e7a752a25bac93a45654ac06e27d5a8e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15283
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The previous change with that intent aligned the framebuffer's
bytes-per-line to 64 instead of 32:
commit 8957dd6b52
Author: Paul Kocialkowski <contact@paulk.fr>
Date: Sun May 1 18:38:04 2016 +0200
tegra124: Align the framebuffer's bytes-per-line to 32
Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14816
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
This will allow kernel to trigger a APM SMI to enable\disable SCI
Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Parse the devicetree and pass the unused device to fsp
for disabling the device function.
BRANCH=none
BUG=chrome-os-partner:54325
TEST=device off in devicetree should disable the device.
Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add support for vboot_platform_prepare_reboot which is called whenever
vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in
such conditions since the platform would no longer be in a resuming
state after reset.
Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15340
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The name 'bpdt_size' is used for a function as well as ia local variable.
As ifwitool is compiled using HOSTCC, there can be an older gcc version
used for the compilation. With gcc version 4.4.7 I get the following
error: declaration of 'bpdt_size' shadows a global declaration
To fix it, rename the function to get_bpdt_size so that names are
unique now.
Change-Id: I47791c705ac4ab28307c52b86940a7a14a5cfef8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15343
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We want to be able to easily change SDRAM clock rate for debugging
purposes. This patch adds configurations for 4 different clock rates.
Same configs are used for all rk3399 boards at 200, 666 and 800 MHz.
Kevin board does not run reliably at 666 MHz, an option for it is
added to run at 300 MHz, this option is available to Kevin only.
There is not much room left in the coreboot romstage section, this is
why the config file for 928 MHz is being added with this patch but is
not included in the code, one of the lower frequency options will have
to be dropped for the higher frequency option to be added.
BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and
gru. Verified that on Kevin the firmware reports starting up
SDRAM at 300 MHz and on Gru at 800 MHz.
Change-Id: Ie24c1813d5a0e9f0f9bfc781cade9e28fb6eb2f1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ef5e4551b79c3f0531f9af35491f2c593f8482f1
Original-Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/353493
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15309
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a purely cosmetic change replacing some of the more prominent
copy and paste sections of the code with compressed versions of the
same.
BRANCH=none
BUG=none
TEST=with the rest of the patches applied stressapptest still runs for
an hour on both Kevin and Gru.
Change-Id: I492e1898e312473d07d9e5eceb3e3e10b48ee35f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: eb8043f96457d090dbbee57097bc1d685e7d32d2
Original-Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/353774
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15308
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Obtain the real-time clock value from the EC on start-up and show the
current time.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits and EC clock set, boot on gru into
Linux shell and check the firmware log:
localhost ~ # grep Date: /sys/firmware/log
Date: 2016-06-20 (Monday) Time: 18:09:16
Change-Id: Id3ef791f546419c4881a891251cbb62d7596884b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 348e9373b0e95a17f5c39ec28a480712e6e45caf
Original-Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351781
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15303
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Duncan Laurie