Commit Graph

52130 Commits

Author SHA1 Message Date
Jay Patel 252e7c5d71 mb/google/rex/Kconfig: Add SMBIOS mainboard version flag
Add GOOGLE_SMBIOS_MAINBOARD_VERSION flag for rex board.

BUG=None
TEST=Verfied board ID for rex using "crossystem" command, giving the
     output as 1.

Without CL:
localhost ~ # crossystem
arch                    = x86       # [RO/str] Platform architecture
backup_nvram_request    = 1         # [RW/int] Backup the nvram somewh
battery_cutoff_request  = 0         # [RW/int] Cut off battery and shu
block_devmode           = 0         # [RW/int] Block all use of develo
board_id                = (error)   # [RO/int] Board hardware revision
clear_tpm_owner_done    = 0         # [RW/int] Clear TPM owner done

With CL:
localhost ~ # crossystem
arch                    = x86       # [RO/str] Platform architecture
backup_nvram_request    = 1         # [RW/int] Backup the nvram somewh
battery_cutoff_request  = 0         # [RW/int] Cut off battery and shu
block_devmode           = 0         # [RW/int] Block all use of develo
board_id                = 1         # [RO/int] Board hardware revision
clear_tpm_owner_done    = 0         # [RW/int] Clear TPM owner done

Signed-off-by: Jay Patel <jay2.patel@intel.com>
Change-Id: I644ed7a948f0094a0be080153d83eaa2e37b8f1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74037
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29 13:19:06 +00:00
Keith Hui 9d1c2d025a Documentation: Add Asus P3B-F
Change-Id: I0cd6141bb8baa082d5558490533649f907f25dd1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-29 13:18:36 +00:00
Keith Hui fc87d0183f Documentation: Add Asus P2B-LS
Change-Id: Ib885c4dd8472ed2b0a61c548f6ef652979a33153
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-29 13:18:13 +00:00
Keith Hui b1cb895c27 nb/intel/i440bx/debug.c: Refactor newlines and save some printk calls
There are two conditions within the config space dump code, one to
print offset, one at the end to put a newline. Tweak the printk
strings so the first conditioned printk does it all and move the
second printk out of the loop to the very end.

Change-Id: Ie9dc744406ba20412892df96720e88e24c3d52bc
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73887
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29 13:17:31 +00:00
Terry Chen b8f1103a32 mb/google/brya/var/crota: Add lp5x memory parts for `K3KL6L60GM-MGCT`
Update the mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.

DRAM Part Name                 ID to assign
K3KL6L60GM-MGCT                5 (0101)

BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I20a12a58d8a3d66a901a14569ca710acba3c05f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73920
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-29 13:16:30 +00:00
Pratikkumar Prajapati 0a71e09cf9 soc/intel/common: Add Intel Trace Hub driver
From Meteor Lake onwards Intel FSP will generate the Trace Hub related
HOB if the Trace Hub is configured to save data in DRAM. This memory
region is used by Trace Hub to store the traces for debugging purpose.
This driver locates the HOB and marks the memory region reserved so
that OS does not use it.

Intel Trace Hub developer manual can be found via document #671536 on
Intel's website.

Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29 13:15:48 +00:00
Pratikkumar Prajapati f5f756d507 drivers/intel/fsp2_0: Add API to find FSP resource HOB by GUID
The API finds the FSP resource HOB for the given GUID.
Returns the pointer to the HOB if found, otherwise NULL

Change-Id: I4ebc9b7d214e5fc731ae45f28e7f5732a7635cbc
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29 13:15:11 +00:00
Subrata Banik b0ddae6a5b soc/intel/cmn/crashlog: Add check for zero based SRAM BAR
This patch adds a check for zero based SRAM base address. It will
help to avoid running into problems if the SRAM is disabled and
the base address register is zero.

TEST=Able to build and boot google/marasov with PCH SRAM being
disabled.

Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29 07:36:18 +00:00
Kilari Raasi b12075876e vc/intel/fsp/mtl: Update header files from 3064_81 to 3084_85
Update header files for FSP for Meteor Lake platform to version 3084_85, previous version being 3064_81.

FirmwareVersionInfo.h:
1. Define INTEL_FVI_SMBIOS_TYPE macro

FSPM:
1. Remove deprecated UPD `BclkSource`
2. Address offset changes

FSPS:
1. Add `CnviWifiCore` UPD
2. Address offset changes

BUG=b:274051289
TEST=Able to build and boot google/rex to ChromeOS.

Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I24dea1a31dbb592f9dea4246a3d490e5d23dca9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29 05:40:28 +00:00
Shon Wang d81d4af8c9 mb/google/nissa/var/yavilla: Update GPIO setting
Configure GPIOs according to schematics.

BUG=b:273791621
TEST=emerge-nissa coreboot

Change-Id: I5a522b59468667d20674d55597cc06975bc12ab5
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2023-03-29 03:07:35 +00:00
Felix Held e30532d0f4 soc/amd/stoneyridge/graphics: introduce defines for constants
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2021a106e0d3a603b1a05296411700ffea32fc8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28 15:16:13 +00:00
Felix Held 1d66ad1cbd soc/amd/stoneyridge: move map_oprom_vendev to graphics.c
Move map_oprom_vendev to graphics.c to match the other AMD SoCs. Also
change the comment style to be more in line with the rest of coreboot
and drop the unneeded line break in the printk call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icc1f3d73fba973413c5a22e2f5ae01bc58bc3e76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28 15:14:35 +00:00
Felix Held 0b03c08223 soc/amd/stoneyridge/Kconfig: use correct VGA_BIOS_ID
Fix the VGA_BIOS_ID IDs to match the PCI IDs in the VBIOS binaries and
the PCI ID Stoneyidge's map_oprom_vendev returns. This fixes the problem
that the display wasn't initialized due to not finding the VBIOS file in
CBFS. This bug in the Stoneyridge Kconfig was unmasked by commit
42f0396a10 ("device/pci_rom: rework PCI ID remapping in
pci_rom_probe").

TEST=Display in Careena lights up again.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d1e6a3a65d7d7b07f49df9ce90620b79d9a2d78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74019
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28 15:13:40 +00:00
Jonathan Zhang ffc5a1ce30 soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCK
Change to use simple device function for setting PMAX_LOCK because
the Sapphire Rapids PCU device is not scanned during coreboot PCIe
bus scan and would see "PCI: dev is NULL!" failure.

Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28 13:28:46 +00:00
Maximilian Brune 60c6a5a6fe util/cbfstool: Add usage information about verbose output
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ica512d21d1cef8ccffbc093016c7a3bfcf901b14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73488
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-28 13:28:15 +00:00
Maximilian Brune 89b4f69746 cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS
Currently ifdtool --validate will not correctly validate the FMAP
against the IFD regions, since it will compare the IFD bios region with
an FMAP region called SI_BIOS.

It's probably a good idea to define default name for the BIOS FMAP
region like we have for 'COREBOOT' or 'FMAP' FMAP region.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28 13:27:57 +00:00
Maximilian Brune 347596ae6e util/ifdtool: Add option to create FMAP template
On systems that do not provide their own *.fmd (Flashmap) file, we
fall back to a default flashmap file. That file however does not contain
the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap.
It can therefore easily happen that the placement of the blobs collides
with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough).
The fmaptool can't catch that, since it does not know of the blobs
placement.

This patch basically maps the regions described in the IFD (Intel
Firmware Descriptor) to the default Flashmap.

Test: Build and see that build/fmap.fmd contains all blobs now (on intel
systems that are supported by the ifdtool)

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I82cb252fff456773af69943e188480a4998736fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28 13:27:50 +00:00
Felix Held a3391e5f7a soc/amd/stoneyridge/Kconfig: select SOC_AMD_COMMON_BLOCK_SVI2
Stoneyridge uses the serial voltage ID 2 standard to tell the VRM on the
board which voltage it wants, so select the SOC_AMD_COMMON_BLOCK_SVI2
Kconfig option to have the corresponding code to decode the raw SVI2
value into a voltage.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7d7031d9ad997a86c18d0e9e7af9a88ddf2d873c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-27 21:00:38 +00:00
jason-ch chen bbf0a418c4 mb/google/geralt: Set up open-drain ChromeOS pins
Set open-drain GPIOs for ChromeOS as input and bias-disable mode.
After applying this patch, the voltage of these pins will become the
expected value 1.8V (previously 1.0V), preventing wrong judgement of
low/high.

Reference document:
MT8188G_GPIO_Formal_Application_Spec_V0.3

BUG=b:274058085
TEST=build pass

Change-Id: I057716df6c59efb84fc395109db022b82ce528c4
Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73963
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:45:24 +00:00
Patrick Huang 69bcf763ab mb/google/skyrim: Add UPD usb3_port_force_gen1 for skyrim
Add UPD usb3_port_force_gen1 for skyrim
The default setting is set to disable
Skyrim -> set default as disable

BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify the setting will be applied on skyrim.

Change-Id: Id53bed82a9fef93b574c3f30830555e02d7f4737
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27 12:31:53 +00:00
Felix Held 70ba567117 soc/amd/common/block/cpu/Makefile: group build targets by stage
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb6087dc44e76ab63bc6b462c3328c23d83ae018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74009
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:14:08 +00:00
Felix Held 00d496f92f soc/amd/common/block/cpu/svi2: drop unneeded core_vid check
A core voltage ID larger than 0xff shouldn't happen, since SVI2's core
VID is only 8 bit long. In order for making it more difficult to use
this function in a wrong way that results in a very wrong voltage being
returned, also return 0 for those invalid core VID values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95417c45db86cd2373879cdad8a07fb9eb8dfdda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74000
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:13:43 +00:00
Patrick Huang 509321f5a8 soc/amd/mendocino: Add UPD to support USB3 force to gen1 by port
Add UPD usb3_port_force_gen1 to support USB3 port force to gen1

BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify USB3 port setting to gen1.

Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27 12:06:31 +00:00
Patrick Huang 292e673276 vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPD
To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1

BUG=b:273841155
BRANCH=None
TEST=Build

Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27 12:06:06 +00:00
Patrick Huang b6436600ca soc/amd/mendocino: Add UPDs for DPTC current limits
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC.
Make sure UPD parameterare are set to be aligned.

BUG=b:245942343
BRANCH=none
TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD.

Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27 12:05:52 +00:00
Felix Held 25b5982d10 soc/amd/stoneyridge/include/msr: add pstate_msr bitfield struct
Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs which will be
used in future patches to generate the P state ACPI packages for the CPU
objects. BKDG #55072 Rev 3.04 was used as a reference.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I944c8598ba95a0333124655c61ef9eba8a7595c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73998
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:03:18 +00:00
Felix Held ca8a8de999 soc/amd: factor out common get_pstate_core_power implementation
Now that all get_pstate_core_power implementations in each SoC's acpi.c
file is identical, factor it out into a common implementation. This
implementation will also work for Stoneyridge which isn't using the
common P state code yet.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iba3833024a5e3ca5a47ffb1c1afdbfd884313c96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73997
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:03:05 +00:00
Felix Held 2c9de49a97 soc/amd: introduce and use get_pstate_core_uvolts for SVI2 and SVI3
Since SVI3 has the CPU voltage ID split into two parts, a serial voltage
ID version specific function is needed to get the raw core VID value.
This will allow making get_pstate_core_power common for all AMD CPUs in
a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71ca88c38b307558905a26cce8be1e8ffc5fbed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73996
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:02:45 +00:00
Felix Held 23a398e001 soc/amd: introduce and use get_uvolts_from_vid for SVI2 and SVI3
Instead of implementing the conversion from the raw serial voltage ID
value to the voltage in microvolts in every SoC, introduce the
SOC_AMD_COMMON_BLOCK_SVI[2,3] Kconfig options for the SoC to select the
correct version, implement get_uvolts_from_vid for both cases and only
include the selected implementation in the build.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I344641217e6e4654fd281d434b88e346e0482f57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73995
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27 12:02:21 +00:00
Jamie Chen fd5d26522c mb/google/brya/var/omnigul: Add WIFI SAR table
Add WIFI SAR table for omnigul.

BUG=b:273170023,b:273652516
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I2db057371754961503cfdc59f21c365fc82672c4
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73940
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-27 08:41:07 +00:00
Fred Reitberger 3b5d9ee516 drivers/spi/spi_flash.c: Prefer 'if' over '#if"
Change preprocessor #if to a regular if and let the compiler optimize
away the unused branch.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7af747812a448064ac6b38686b8bd616a755932e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-26 21:02:35 +00:00
Yidi Lin 13ed70f10b mb/google/geralt: Set orientation to LB_FB_ORIENTATION_BOTTOM_UP
Set orientation to LB_FB_ORIENTATION_BOTTOM_UP to align the volume
up/down direction with menu up/down in FW screen.

BUG=b:274749478
TEST=see FW screen in portrait mode.
TEST=volume key behaves as expected

Change-Id: If32859c4bf256c97147622ff04a17fc2ec80303d
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-26 21:02:12 +00:00
Morris Hsu c826c11b50 mb/google/brask/var/constitution: Add TcssAuxori for constitution
Enable SBU orientation handling by SoC for both USBC port2 and USBC
port3.
Constitution USBC port1 has retimer but USBC port2 and USBC port3 don't,
they do not flip the data lines, hence we need to set bits for USBC ports.

Change-Id: I4c5dfdba6c38c6e2f308b281ed316bb687ad8d8b
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-26 21:01:58 +00:00
Sean Rhodes ac69ce9122 mb/starlabs/*: Remove sleepstates.asl
Remove the sleepstates.asl as it was written for SOCs pre-Skylake
and not needed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I46fe934c2a50b3d61575f66f0881ab6754fe8dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-03-26 21:01:39 +00:00
Fred Reitberger 6cbd9cfbcb mb/amd/birman/Kconfig: Select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
Birman requires 4-byte addressing for flash.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id732129cfc14bb47e8f3d7f3de479815e040ea16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-26 20:54:08 +00:00
Fred Reitberger 52be7f6b10 drivers/spi: Add SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
Add Kconfig option to force 4-byte addressing mode.

Some platforms require the flash to stay in 4-byte addressing mode where
it expects 4-byte addresses on regular commands.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2e41da2a78285c23c1c1d97eaf3969749812327b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-26 20:53:48 +00:00
Fred Reitberger 75e720bf02 mb/amd/birman: Move EC FW to FMAP
Move EC FW from a CBFS file to an FMAP entry and rename the EC signature
section to EC_SIG.

An offset of (16M - 512K) was chosen to line up the EC FW before the
RW_MRC_CACHE.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9b19d92043790b10acd20fbfdf394d5bd67b8295
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-26 20:52:00 +00:00
Subrata Banik 36ca7b3104 soc/intel: Move USB PORTSC definition into IA common code
This patch moves USB Port Status and Control (PORTSC) Reg definition
into IA common code to allow other SoC code to reuse it without
redefining the same for each SoC.

TEST=Able to build and boot google/taeko where USB wake is working.

Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-26 19:44:15 +00:00
Jonathan Zhang 532e8c059e soc/intel/xeon_sp/chip_common.c: Probe all buses in attach_iio_stacks()
For some Xeon-SP (such as SPR-SP), more buses should be probed.

Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-25 16:42:06 +00:00
Tim Chu 5c1964058f soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP support
Add support for Intel SPR-SP to uncore_acpi.c.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-25 16:33:36 +00:00
Fabian Groffen ab84353356 mb/asrock/b75pro3-m: Remove cpu_fan_tach_src from CMOS layout
Commit 65c456227e (mb/asrock/b75pro3-m: Add CMOS layout/defaults and
vbt.bin) introduced CMOS settings for selecting CPU_FAN{1,2}, but this
code was never implemented.  Remove the fake setting for it.

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ic2f4aa42f9cfd77defc2a11e16643690356bc26b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-25 16:01:05 +00:00
Subrata Banik 1653b6f2a2 mb/google/rex: Use HI-556W for Proto 1 SKUs
This patch drops the UFC sensor OV2740 (reused from the Brya chassis)
support for Rex and added support for Rex specific UFC sensor HI-556W.

BUG=b:269499723
TEST=Verified UFC is working on google/rex Proto 1.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6b8ac08adec351a103ac1764d974db4881dc4d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70225
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-25 05:42:06 +00:00
Felix Held 1f1ae8ef05 soc/amd/common/include/cppc: remove cppc_config forward declaration
The included acpi/acpigen.h provides the cppc_config struct and nothing
in this header file is using the cppc_config struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia91fd4105e6872d812f595447783d02a0dd1568b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73993
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-25 00:36:16 +00:00
Felix Held 797894d0cc soc/amd/common/include/cppc: rename include guard
When the code was made common in commit 8f7f4bf87a ("soc/amd/cezanne,
common: factor out CPPC code to common AMD SoC code"), the include guard
wasn't renamed accordingly, so do that now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9eefe2065fae31e97aa4e6710008a6f9712bed40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73992
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-25 00:36:05 +00:00
Felix Held 3f2844fb1e soc/amd/*/include/msr: add version number to SERIAL_VID_* define names
Picasso and Cezanne use the serial voltage ID 2 standard to communicate
the CPU voltage to the voltage regulator module on the mainboard, while
Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for
this. Both standards encode the voltage in a different way, so add the
serial VID version number to the defines to clarify for which version
the define is.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-24 23:17:02 +00:00
Felix Held 6a6d524b0a soc/amd/mendocino: add and use missing cpu_vid_8 pstate_msr field
Mendocino uses the SVI3 standard for CPU core voltage control which uses
9 data bits instead of the 8 in the SVI2 case and also calculates the
actual voltages with a different formula. The Mendocino code uses the
correct formula since commit 8d2bfbce23 ("soc/amd/sabrina/acpi:
Correct VID decoding on Sabrina"), but the MSR definition in the PPR
hasn't been updated to show the additional bit. The definition of the
register that is mirrored by these MSRs descries this 9th CPU voltage ID
bit though. Since this bit is expected to be zero, this shouldn't cause
a change in behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I05acd239300836a34e40cd3f31ea819b79766e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73969
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-24 23:16:41 +00:00
Angel Pons ff23f455c4 mb/prodrive/atlas: Configure some FSP settings
Program some FSP settings as requested by Prodrive.

Change-Id: I04548e5eddc8a6be3a03b5dd9062470b4ef85adb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24 16:40:01 +00:00
Angel Pons 56c1c4dff9 mb/prodrive/atlas: Implement initial VPD support
Atlas stores VPD (Vital Product Data) in an I2C EEPROM, which is only
connected to the EC. In order for the host (x86) to be able to access
the VPD, the EC reads the EEPROM contents into a buffer in EC RAM and
provides the host with read-only access to this EC RAM buffer through
EMI (Embedded Memory Interface) 0.

The VPD layout is designed to be extensible yet backwards compatible.
The code in coreboot uses the revision field to know which fields are
valid, and will populate the rest with fallback values.

Use the serial number and part number in VPD to populate SMBIOS tables.

Change-Id: I2d3d70fee22548daa73ef98af56c98e950dc5e9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24 16:39:17 +00:00
Angel Pons 964079f77c mb/prodrive/atlas: Add support to read from EC EMI
Implement initial support for EMI (Embedded Memory Interface), which
Microchip describes as "a standard run-time mechanism for the system
host to communicate with the Embedded Controller (EC) and other logical
components". EMI allows the host to access regions of EC memory without
requiring any assistance from the EC.

For now, Atlas only uses EMI 0. This change enables EMI 0, subsequent
commits will read data from it.

Change-Id: Ia899ae71e97f9fc259397dfb5fb84ca06545f5d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24 16:36:42 +00:00
Tim Chu 3ba1621dab soc/intel/xeon_sp/smihandler.c: enable support for spr-sp
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC
instead of UBOX_DEV_PMON.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-24 16:07:23 +00:00