Currently (EVT) this is a pullup resistor on the board (i.e. always in
dev mode). Future builds it will be pull down and require servo or HW
modification to control. Either way, this change means the FW should
acknowledge it.
BUG=chrome-os-partner:38663
TEST=Manually verified that servo devmode switch toggles this GPIO. requires FW signing to verify GPIO is observed and dev mode active.
BRANCH=none
Change-Id: Ib05216992abc5f6175fe7395471bd379f185b61f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 702c8d222a3d19d6b8db89d122dcdf594c85da99
Original-Change-Id: I1d0f31819b9f7a1ab63deac52bcaf0b996499b0c
Original-Reviewed-on: https://chromium-review.googlesource.com/263529
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Jonathan Dixon <joth@chromium.org>
Original-Commit-Queue: Jonathan Dixon <joth@chromium.org>
Reviewed-on: http://review.coreboot.org/9928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch switches the mainboards with board id straps
to use BOARD_ID_AUTO instead of BOARD_ID_SUPPORT.
On urara, which does not have those straps, the option is
removed. (And re-added for urara derivatives through setting
the config option BOARD_ID_MANUAL
BRANCH=none
BUG=chrome-os-partner:37593
TEST=emerg-nyan_big coreboot, emerge-urara coreboot, emerge-buranku coreboot
Change-Id: I5ac4024c6f1f9b9d7a5179d88722c69b23b82bbd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 22a470698f9c9ed275aa8150a5bb8d8cf368b050
Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Change-Id: I48c291ad6f255a28c833bebc2638bfafa2782e74
Original-Reviewed-on: https://chromium-review.googlesource.com/262935
Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: http://review.coreboot.org/9906
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Invoke the function which copies MAC addresses from VPD into the
coreboot table and calibration data into CBMEM.
BRANCH=none
BUG=chrome-os-partner:36584
TEST=with the rest of the patches applied observed that the MAC
addresses from VPD get copied into the appropriate kernel device
tree nodes.
Change-Id: I68e2b73520853ef2d3249ca12ee87669fd01f442
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12f935098c50e2df345748d3b71cee2152acd422
Original-Change-Id: I6e1483d33480d13380ade2dddae6c92fd3f1f881
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262844
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288
(veyron) boards. This increases flash read speeds (and thereby decreases
boot time) significantly, but we don't seem to get any more increases by
going even higher. We have also seen occasional read failures at higher
speeds in certain configurations, so this frequency seems to be the best
option.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted on Jerry with Servo attached.
Change-Id: I9bdb62eff169fe2be33558caafe9891668589372
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b
Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262645
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The hardware initialization is now split in basic
initialization (MIPS and system PLL, system clock,
SPIM, UART), and initialization of other hardware
blocks (USB, I2C, ETH). The second part uses board ID
information to select setup that is board specific
(currently only I2C interface is selected through
board ID).
BRANCH=none
BUG=chrome-os-partner:37593
TEST=tested on bring up board for both Urara and Concerto;
to simulate the use of Concerto (I2C3) DIP SW17 was
set to 0.
it works with default settings on Urara
Change-Id: Ic5bbf28ab42545a4fb2aa6fd30592a02ecc15cb5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f2b3db2e7f9fa898214f974ca34ea427196d2e4e
Original-Change-Id: Iac9a082ad84444af1d9d9785a2d0cc3205140d15
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/257401
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9888
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The code to calculate the RK3288 SPI controller's internal clock divisor
is wrong: it assumes that the divisor register was an "n-1" divisor when
it actually isn't (due to some misleading kernel code that was copied in
here). This means that all SPI clocks are currently running lower than
expected.
This patch fixes the calculation and changes all callers such that the
effective speeds stay the same.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted Jerry with and without the patch, dumping the divisor for
flash and EC clocks. Made sure it stays the same.
Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb
Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262269
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the serial number from VPD on ryu.
BRANCH=none
BUG=chrome-os-partner:37813
TEST=devicetree is populated with "compatible", "hardware",
and "serialno" properties
Change-Id: I1e84933a01a34028a062d31aad026f91c3bd29e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18cefb655651c9097ff7f2ef3cb735efbbe32370
Original-Change-Id: I14439c37df0fde7f2328c7caae1adf6a122e8f5f
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260646
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The old parameters are wrong. K4B8G1646Q: rank = 2, row = 15 is right.
BUG=None
TEST=Boot from veyron
BRANCH=None
Change-Id: I41848c158f3ea028035cc8c0d969a4a449390a54
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 601ba06c636ff0f0779e6ef9357b53060a1ec19b
Original-Change-Id: I5bc6798890b3ba0f5134d048ae6bbf2bfd696676
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/260483
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Paul Ma <magf@bitland.com.cn>
Reviewed-on: http://review.coreboot.org/9866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
in depthcharge we will use "backlight" gpio which in lb_gpio table
to control backlight, we use lcd_bl before, but it will not meet
the backlight power sequence, so we change it to bl_en.
BUG=chrome-os-partner:37348
TEST=Boot from speedy, and backlight work well
BRANCH=None
Change-Id: I19e488c7d3f1fe5cb91f8a93fae6b848f58b36b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb594ce612e1cedeabced4531fbd954f3698da98
Original-Change-Id: Ib0dac7c48bce7d0b28ec287b32d8c5bad575893f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/259900
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Concerto board does not have the means of detecting the identity of
the device it is controlling. But it is very beneficial to be able to
use the same firmware image on Concerto boards running different
devices.
The suggested solution is to keep the device identity as a string in a
raw CBFS file called 'board_id'.
With this patch coreboot maintains a table of possible board name
strings and their matching board IDs.
BRANCH=none
BUG=chrome-os-partner:37593
TEST=verified that without the board id file addition the default
Board ID of zero is used. Adding the file as follows:
echo -n 'concerto' > /tmp/bid
cbfstool /build/urara/firmware/image.serial.bin add -f /tmp/bid \
-t raw -n 'board_id'
results in firmware reporting board ID setting of 1.
board_id: failed to locate CBFS file board_id
board_id: name urara, ID 0
Change-Id: I5a02192740dc94b1ea8090092cc325fe0ac42aa6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f41f9b07f155f0c719c36e0cd93081205624557e
Original-Change-Id: I8341782005b101be78f5c9a6b375c8f73179c1ad
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/257170
Reviewed-on: http://review.coreboot.org/9856
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This add hynix-2GB SDRAM(H5TC4G63AFR-PBA), whose timing is the same as
H5TC4G63CFR-PBA, to veyron boards.
BUG=None
BRANCH=veyron
TEST=build on mighty and boot on mighty board with ram-id reworked
Change-Id: I3ae5e65e60e18414cf4de6fbcc5bed736b1492de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b22029f9b05ebb9a775266a7e3aae38b50c1883a
Original-Change-Id: If17fb002f2816990e1706833b37ac6be345e540b
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256307
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/9848
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The I2C MFIO setup function now supports all interfaces.
Also, the API for the clock setup function changed to support
all interfaces.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; all I2C interfaces
were tested with the TPM and they all work properly.
BRANCH=none
Change-Id: I6dfd1c4647335878402cabb2ae512d6e3737a433
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8a7ffb54e3f5092c9844b9b502949d3cfc053d1
Original-Change-Id: Ibd67c07acf3d1d9c594faa8ced5ab56d9abb2e40
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256362
Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9840
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; all I2C interfaces
were tested with the TPM and they all work properly.
BRANCH=none
Change-Id: I02202585140beb818212c02800f6b7e4966a922a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d
Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256361
Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch removes quite a bit of code duplication between cpu_to_le32()
and clrsetbits_le32() style macros on the different architectures. This
also syncs those macros back up to the new write32(a, v) style IO
accessor macros that are now used on ARM and ARM64.
CQ-DEPEND=CL:254862
BRANCH=none
BUG=chromium:444723
TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu,
Storm and Urara. Booted on Jerry. Tried to compare binary images...
unfortunately something about the new macro notation makes the compiler
evaluate it more efficiently (not recalculating the address between the
read and the write), so this was of limited value.
Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b
Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254866
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This applies the same hack to Danger and Brain as on Rialto which
allows us to remove the EC-related sections from their respective
flashmaps.
BUG=none
BRANCH=veyron
CQ-DEPEND=CL:255669
TEST=built and booted on Brain w/ depthcharge and mosys changes,
was able to read vbnv data from userspace
Change-Id: I95715d59a21cd081ac4a3a2216576ede5620f1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4de4273be9ac80ca77a34bc076d1f265fbb94e9f
Original-Change-Id: I6c2041e8c17ab157599255a505aaef5e2447a241
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255780
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We found that we should better keep ODT off for LPDDR3 on our boards.
BRANCH=veyron
BUG=chrome-os-partner:37346
TEST=Boot veyron_speedy normal
Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599
Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255381
Reviewed-on: http://review.coreboot.org/9830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds all SDRAM configurations currently in use for any Veyron
board to all boards. In the future we might decide that we want to reuse
known good memory from one board on another, and having all of these in
there already might help us avoid a firmware rev. We can still
differentiate them later if the need ever arises.
Not touching Rialto since it already decided to go its own way and
replace an existing RAM code with it's own 1GB configuration. Also
adjusting the names of the recently added DDR3 4GB configs to fit the
existing scheme.
Includes changes from "veyron: The ODT function is disabled LPDDR3".
BRANCH=veyron
BUG=None
TEST=Compiled all Veyron boards, booted on Jerry.
Change-Id: I817efd4b467a5a9587475a82df207048173e7bd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 36d3fe138b154a16700e3c7adbb33834ff1c5284
Original-Change-Id: I4d037967dcb5cbd6b2b82f347f6b19541559b61a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255665
Reviewed-on: http://review.coreboot.org/9829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
add the K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3 inf file,
and use ram_id 1110 correspond to K4B8G1646Q-4GB ddr3
use ram_id 1111 correspond to H5TC8G63XXX-4GB ddr3
BUG=None
TEST=Boot veyron_jerry normal
BRANCH=None
Change-Id: I3398516a9f2c2e44c9f5d08d0a3ab6e76b5c6f5f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b8dfc455bb93c2daf567e3b6e39c0a715e44311c
Original-Change-Id: I90250cb84eb140f93c4fc655fb3b90584dd515c0
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/255010
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9826
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change switches all mainboard vendors and mainboards
to be autoincluded by Kconfig, rather than having to be mentioned
explicitly.
This means, vendor and mainboard directories are becoming more
"drop in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree mainboards / components
to be built with a given coreboot version (given that the API did
not change)
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a
Reviewed-on: http://review.coreboot.org/9295
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Compile in support for the STM flash devices.
BRANCH=storm
BUG=chrome-os-partner:33489
TEST=verified that both spansion and stm flash devices boot as
expected.
Change-Id: Ib616b2b52d29b20b4447c92115181a92c524ac39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34c0147b45551e9161e3f0e342a753907f27f9ae
Original-Change-Id: I922afb91cc3ac5bf459d9746817d7677986b93cd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248993
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Storm devices' recovery button is overloaded. Pressing it when the
system is running is supposed to reset the device. To trigger recovery
mode the button must be held pressed for at least 5 seconds after
reset.
Currently interpreting the recovery button state is the responsibility
of the board (vboot gets a consolidated state, which is a combination
of several conditions), so the simplest way to implement this feature
is to make the board follow the recovery button state.
In case the button is not pressed when it is first sampled, its state
is saved immediately and no recovery request is reported. In case the
button is pressed when it is first sampled, the board code keeps
polling it up to 5 seconds and acts accordingly.
BRANCH=storm
BUG=chrome-os-partner:36059
TEST=tried starting a whirlwind with recovery button pressed for
various durations, it entered recovery mode when the button was
pressed longer than 5 seconds.
Change-Id: Icb3250be7c2a76089c070acd68cb521d1399e245
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45e7265bc760944f93dd98903d39d2b30aa96365
Original-Change-Id: Iab3609ebce3a74e3d0270775b83f3cf03a8837ca
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/251711
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/9761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GSBI driver is extended to be able to program the CTRL reg for any given
GSBI block. The NS and MD registers programming is made more readable by
programming the M, N, D and other bits of the registers individually.
Defined configure structs for each QUP block to be able to track the init
status for each qup.
Configured GPIO8 and GPIO9 for I2C fuction.
BRANCH=chromeos-2013.04
BUG=chrome-os-partner:36722
TEST=Booted up storm P0.2, verified that the TPM on GSBI1 still works.
Change-Id: I17906beedef5c80267cf114892080b121902210a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07bc79211770decc1070c3a88874a4e452b8f5bc
Original-Change-Id: I841d0d419f7339f5e5cb3385da98786eb18252ad
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/250763
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Trybot-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a clock control driver to initialize the clock tree inside the
low-power audio subsystem. Depthcharge builds up on this to enable
audio function on storm.
The clock is hardcoded for 48KHz frame rate, two 16 bit channels.
BRANCH=storm
BUG=chrome-os-partner:35247
TEST=with depthcharge patches applied and Using depthcharge CLI audio
test program verified that the target generates sensible sounds
audio 100 100
audio 1000 5000
Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760
Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f
Original-Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248830
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: http://review.coreboot.org/9758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This brings brain, danger, and rialto up to parity with other
veyron platforms as far as eventlog functionality is concerned.
BUG=chrome-os-partner:34436
BRANCH=none
TEST="mosys eventlog list" shows events (tested on Brain)
Change-Id: I186c5d18e5351c0eaf08ffecfd87506283c44b19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1764bc53147718031231a6d125a4a1a96c4c6a8f
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ief09299965f6f21bc5a40cef31cde61344025c2a
Original-Reviewed-on: https://chromium-review.googlesource.com/239979
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This applies a previous patch ("chromeos: Provide common watchdog
reboot support") to some veyron platforms that were missing it.
BUG=none
BRANCH=none
TEST=built and booted on Brain
Change-Id: I3eb431a57367b8f885844e4353a78f77515f5195
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0c87dd4217917a35817c719efe43dd4ec442df0
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I2861939655a995d309847f64cecd974a740fae37
Original-Reviewed-on: https://chromium-review.googlesource.com/245633
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9754
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
we will use dvs to adjust the voltage in kernel, if device reset
by watchdog in kernel, the dvs gpio may not reset, and we use the
i2c to adjust rk808 voltage in coreboot, so it may failure. so we
move the reboot_from_watchdog() before the rk808 setting.
BUG=None
TEST=Boot from speedy
BRANCH=None
Change-Id: I809c63153d49680d9c84462aafd7bae09106fa6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76efb4b0196eecc84664a4c5dce2221152a39c0a
Original-Change-Id: I92b5c6413bbffe30566178de89df1f9683790982
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/244289
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Many ChromeOS devices use a GPIO to reset the system, in order to
guarantee that the TPM cannot be reset without also resetting the CPU.
Often chipset/SoC hardware watchdogs trigger some kind of built-in
CPU reset, bypassing this GPIO and thus leaving the TPM locked. These
ChromeOS devices need to detect that condition in their bootblock and
trigger a second (proper) reboot.
This patch adds some code to generalize this previously
mainboard-specific functionality and uses it on Veyron boards. It also
provides some code to add the proper eventlog entry for a watchdog
reset. Since the second reboot has to happen before firmware
verification and the eventlog is usually only initialized afterwards, we
provide the functionality to place a tombstone in a memlayout-defined
location (which could be SRAM or some MMIO register that is preserved
across reboots).
[pg: Integrates
'mips: Temporarily work around build error caused by <arch/io.h> mismatch]
BRANCH=veyron
BUG=chrome-os-partner:35705
TEST=Run 'mem w 0xff800000 0x9' on a Jerry, watch how a "Hardware
watchdog reset" event appears in the eventlog after the reboot.
Change-Id: I0a33820b236c9328b2f9b20905b69cb934326f2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fffc484bb89f5129d62739dcb44d08d7f5b30b33
Original-Change-Id: I7ee1d02676e9159794d29e033d71c09fdf4620fd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242404
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: c919c72ddc9d2e1e18858c0bf49c0ce79f2bc506
Original-Change-Id: I509c842d3393bd810e89ebdf0dc745275c120c1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242504
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9749
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:34436
BRANCH=none
TEST=Built and booted on pinky w/ depthcharge fmap patch,
used mosys to verify that eventlog entries get populated:
entry="0" timestamp="2015-01-06 13:45:33" type="Log area cleared" bytes="4096"
entry="1" timestamp="2015-01-06 13:45:33" type="System boot" count="0"
entry="2" timestamp="2015-01-06 13:45:33" type="Chrome OS Developer Mode"
Change-Id: I74ba8b271328453c8b91f11e7858754a80806c31
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 197010f057f4835a30ed2e71f47ca51fc181afe4
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I19cb884be5c3e00975599e96e0223e33d32e7c0d
Original-Reviewed-on: https://chromium-review.googlesource.com/238830
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9644
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
we use Kconfig define sdram size before, but there may use
different sdram size in the same overlay, so we must detect
sdram size at runtime now. If we use 4G byte sdram, we can
use[0x00000000:0xff000000], since the [0xff000000:0xffffffff]
is the register space.
BUG=chrome-os-partner:35521
TEST=Boot from mighty
BRANCH=None
Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898
Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/243139
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I always had that TODO comment in there but I had already forgotten what
I even meant by it. It's really just a simple cleanup... this function
is (currently) veyron-specific and doesn't belong in common code.
BRANCH=veyron
BUG=None
TEST=Booted Jerry.
Change-Id: Iccd6130c90e67b8ee905e188857c99deda966f14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d188398704575ad2fedc2a715e609521da2332b0
Original-Change-Id: I6ce701a15a6542a615d3d81f70aa71662567d4fa
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241190
Reviewed-on: http://review.coreboot.org/9733
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current display init code causes Brain to crash when trying
to allocate resources. This just avoids doing display init if a
config variable is set. Once code has been implemented to properly
setup different types of displays we can get rid of this hack.
BUG=none
BRANCH=none
TEST=built and booted (to depthcharge) on Brain, compiled for
pinky with FEATURES=noclean and ensured config variable is 0
Change-Id: I9a7266c6bff5b7a6eb05b2b21fb65797bee392d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 804632ca67eaaf4174ca597d83b8923cb9abd1b7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I04c9e8181c58fa0608fd20776fa8c4798a023474
Original-Reviewed-on: https://chromium-review.googlesource.com/235922
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch activates the chip driver for Winbond SPI flash (which,
incidentally, looks 99.9% the same as the Gigadevice driver but still
requires some extra 500+ bytes of object code... there's definitely room
for improvement here). Shuffle around rk3288 memlayout to make a little
more room in the bootblock.
BRANCH=veyron
BUG=chrome-os-partner:34176
TEST=Booted Pinky. Checked bootblock and verstage memsz of final binary
and noticed that both only have less than 500 bytes left against their
memlayout boundary. The next piece of code we add will cause some
serious headaches...
Change-Id: I97ea6ac334104e4219e310afc557c164b2ff19d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8769e5a34ad3cd417132646fbb58ff51c29fb640
Original-Change-Id: Id2f1204c30aa28251cf85cb80d7ca44947388dba
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236977
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9719
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
we use the delay 200ms to meet the edp power timing request before,
it waste time, so we use the HPD function to detect the edp panel now.
In previous version, the hardware may not support the edp HPD function,
so in the code it will spend 200ms to detect hpd single, if it don't get
the hpd single, it will contiue the edp initialization process, to compatible
all of the hardware version.
BUG=chrome-os-partner:35623
TEST=Boot from Mighty, and display normal
BRANCH=None
Change-Id: I82c6a80e37fa42eef3521e6ebbf190d7e80fcece
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 7a5343eb9af12cae9a15284217762a91ae24bac6
Original-Change-Id: I21c0ef6ce4643e90a192d8b86659264895b5fda9
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/242792
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: http://review.coreboot.org/9659
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
backlight timing: LED_VCC->LED_PWM->LED_EN, we modify the
code to meet the timing.
BUG=chrome-os-partner:36201
TEST=Boot from jerry, and scope the backlight timing
BRANCH=None
Change-Id: I6bfa6af176400086e4af0112a63127c1152ca70e
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 52ac0b2944cea7dc860bfea12fe44851436bb7f7
Original-Change-Id: I6c53a822410ad706383c6d9fa2b5f0437775f710
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/244639
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The recovery button on Rialto should be GPIO 255, the LED Push Key.
Note we want to keep the recovery button on servo functional because
many protos are not assembled and developers can't "push" the push key.
The GPIO passed to payloads (and kernel) is only mapped to Push Key.
BUG=none
TEST=emerge-veyron_rialto coreboot chromeos-bootimage
BRANCH=veyron_rialto
Change-Id: I66f94cf232caa53a3b28db517620e4b6e9b9af0e
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 66ee55f6312efaeb337eb2881cd5eff5365b4105
Original-Change-Id: I0a7ebeed6506fbd938084c9a078a7cf1c7b914b9
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/244515
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9657
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
