This patch reduces the thermal time window to 100 milliseconds
for fast throttling action at prochot.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the thermal time
window value.
Change-Id: If79d213cb8e19277ffdb882267d2f8672df93446
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17384
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This variable can be set in a debugger (e.g. Spike)
to finely control which traps go to coreboot and
which go to the supervisor.
Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17404
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The riscv 1.9 standard defines a textual config string to be passed
to kernels and hypervisors. Change the payload function to pass
this string in a0.
Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17254
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
These functions will allow us to remove hardcodes,
as long as we can verify the qemu and lowrisc targets
implement the configstring correctly. Hence, for the
most part, we'll start with mainboard changes first.
Define a new config variable, CONFIG_RISCV_CONFIGSTRING,
which has a default value that works on all existing
systems but which can be changed
as needed for a new SOC or mainboard.
Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17256
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
I've tested this with commits to come later.
This is from the lowrisc bbl distribution, 87588c4,
with fixes so it builds.
Change-Id: I87893638872259c94d6972e1971578b633155e7e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17255
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The end of firmware notification is currently not being tracked
so it's hard to get good data on how long it takes. Update the
code to provide timestamp data as well as post codes.
BUG=chrome-os-partner:56656
Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17373
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.
Depthcharge payload loading was sped up by 75ms using this.
BUG=chrome-os-partner:56656,chrome-os-partner:59682
Change-Id: Iba87a51a05559d81b8e00fa4f6824dacf7a661f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17372
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Certain platforms have a poorly performing SPI prefetcher so even if
accessing MMIO BIOS once the fetch time can be impacted. Payload
loading is one example where it can be impacted. Therefore, add the
ability for a platform to reconfigure the currently running CPU's
variable MTRR settings for the duration of coreboot's execution.
The function mtrr_use_temp_range() is added which uses the previous
MTRR solution as a basis along with a new range and type to use.
A new solution is calculated with the updated settings and the
original solution is put back prior to exiting coreboot into the OS
or payload.
Using this patch on apollolake reduced depthcharge payload loading
by 75 ms.
BUG=chrome-os-partner:56656,chrome-os-partner:59682
Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17371
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default register count calculations are leading to higher
frequencies than expected. Provide an alternative method for
calculating the register counts by utilizing the rise and
fall times of the bus. If the rise time is supplied the
rise/fall time values are used, but the register overrides
take precedence over the rise/fall time calculation. This
allows platforms to choose whichever method works the best.
BUG=chrome-os-partner:58889
Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Since tlcl library is used other than just vboot driver, ensure that the
library is initialized only once per stage.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified in recovery mode on reef, tlcl library is initialized only
once in romstage.
Change-Id: I6245fe9ed34f5c174341b7eea8db456b45113287
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
commit 80EF7B7 [IT8772F: Clean up it8772f includes and add a LED API]
broke power LED operation when it incorrectly transferred
values from the old function (it8772f_gpio_setup) to the new one (
it8772f_gpio_led). Restore the correct values so power LED illuminates
when powered on.
Change-Id: I99a38351bb52063fafa7436e6397a8da7fc1e952
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17266
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This function is not used anywhere else in the code.
BRANCH=none
BUG=none
TEST=reef and kevin boards (using tpm1.2 and tpm2.0 respectively)
build successfully.
Change-Id: Ifcc345ae9c22b25fdcfc2e547e70766021d27e32
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Have a common romstage.c file to prepare CAR stack guards.
MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.
Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression, S3 resume not working on sandy/ivy after commit
9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible
There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup
being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes
this delay by removing need of this backup entirely.
Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15248
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.
sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17361
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Snappy is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The apollolake and skylake had duplicate stanzas of code for
initializing the i2c buses. Additionally, they also had very
similar structures for providing settings for the i2c speed
control. Introduce a new struct lpss_i2c_bus_config and
utilize it in both apollolake and skylake thereby removing
the need for SoC-specific structres. The new structure is
used for initializing a bus fully as the lpss i2c API is
simplified in that lpss_i2c_init() is only required to be
called. The struct lpss_i2c_bus_config structure is passed
in for both initializing and filling in the SSDT information.
The formerly exposed functions are made static to reduce the
external API exposure.
BUG=chrome-os-partner:58889
Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17348
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In preparation of merging the lpss i2c config structures on
apollolake and skylake move the i2c voltage variable to its
own field. It makes refactoring things easier, and then there's
no reason for a separate SoC specific i2c config structure.
BUG=chrome-os-partner:58889
Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified kernel is able to talk to the device. Even without the
digitizer, no issues observed with the kernel.
Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17343
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This brings the I2C frequency down to 400kHz which is spec for fast
I2C.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified frequency in kernel.
Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wacom I2C driver can be used by devices other than
touchscreen. e.g. digitizer. So there is no need to name the driver
with touchscreen specific attributes. Only a separate descriptor name
is required that needs to be set by mainboard correctly.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Compiles successfully.
Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Program I/O expander connected on I2C bus 4
Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This space is read/updated only in recovery mode.
1. During read phase, verify if the hash of MRC data read from
RECOVERY_MRC_CACHE matches the hash stored in TPM.
2. During update phase, calculate hash of training data returned by MRC
and save it in TPM.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified MRC data hash comparison and update operation on reef.
Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Add a new index for recovery hash space in TPM - 0x100b
2. Add helper functions to read/write/lock recovery hash space in TPM
3. Add Kconfig option that can be selected by mainboards that want to
define this space.
4. Lock this new space while jumping from RO to RW.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified use of recovery hash space on reef.
Change-Id: I1cacd54f0a896d0f2af32d4b7c9ae581a918f9bb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17273
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
mainboard/thomson/ip1000.
Change-Id: Id7b979d2539d4a80609a60464527939c4d449822
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17308
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/supermicro/h8qme_fam10.
Change-Id: Ia03c205ce498eadf8a34749a6a21fb2d0b29c840
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/supermicro/h8qgi.
Change-Id: I6cf123272283edbf89e854e4aa1a15a2d566133e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/roda/rk9.
Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17302
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/roda/rk886ex.
Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17301
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/rcs/rm4100.
Change-Id: I8b242eefe796cd93337177fc694ea42c57c53f08
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17300
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.
sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This driver is required for reading and updating TPM space for recovery
MRC data hash in romstage.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles successfully for reef.
Change-Id: I8edb7af13285a7a192e3d55fc6a11cfe12654bf9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
1. Add RECOVERY_MRC_CACHE region to reef FMAP.
2. Implement helper function for getting event for recovery mode with
memory retraining.
3. Select HAS_RECOVERY_MRC_CACHE.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified recovery mode behavior with and without memory training
request on reef.
Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or
RECOVERY_MRC_CACHE based on the boot mode.
- If normal mode boot, use RW_MRC_CACHE, if available.
- If recovery mode boot:
- Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is
requested explicity with retrain memory request.
- Use RECOVERY_MRC_CACHE otherwise.
2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot
modes. Check if both are present under one unified region and protect
that region as a whole. Else try protecting individual regions.
3. Update training data in appropriate cache:
- Use RW_MRC_CACHE if normal mode.
- Use RECOVERY_MRC_CACHE if present in recovery mode. Else use
RW_MRC_CACHE.
4. Add proper debug logs to indicate which training data cache is used
at any point.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified that correct cache is used in both normal and recovery
mode on reef.
Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Add new function vboot_recovery_mode_memory_retrain that indicates if
recovery mode requires memory retraining to be performed.
2. Add helper function get_recovery_mode_retrain_switch to read memory
retrain switch. This is provided as weak function which should be
implemented by mainboard just like {get,clear}_recovery_mode_switch.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified behavior of recovery mode with forced memory retraining on
reef
Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sumeet Pawnikar