Commit Graph

2589 Commits

Author SHA1 Message Date
Carl-Daniel Hailfinger 3f09561ec4 Add more infrastructure for flashrom ICH9 support.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:51:22 +00:00
Stefan Reinauer 58a1cc1d34 fix license mentioning in manpage (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:47:32 +00:00
Stefan Reinauer 9f7af6ef40 trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:22:59 +00:00
Stefan Reinauer d466e6a874 trivial patch to fix options. Thanks to Uwe Hermann for the hint!
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 13:52:50 +00:00
Claus Gindhart e173f9904c Add the Intel 6300ESB as known chipset to the chipset struct enables.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:22:38 +00:00
Carl-Daniel Hailfinger 42aab08d84 Fix crash caused by division by zero for unknown flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:09:31 +00:00
Carl-Daniel Hailfinger 68db3a2bdc Check the JEDEC vendor ID for correct parity. Flash chips which can be
detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:03:06 +00:00
Stefan Reinauer b69e46bca3 Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
have different register meanings, so they get their own lookup tables.

This is a trivial patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 11:38:22 +00:00
Carl-Daniel Hailfinger 1984067a86 Add lots of ATMEL SPI flash chips to flash.h.
Add a few flashchips already mentioned in flash.h to flashchips.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 04:27:02 +00:00
Carl-Daniel Hailfinger b77fb6bd52 flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 23:03:12 +00:00
Stefan Reinauer 03646bebbe Add new revised inteltool that dumps all kinds of chipset information and drop old
gpio_dump utility.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 22:14:21 +00:00
Myles Watson 56cc34a9a7 This is a trivial patch which fixes the tint build by removing the extra
typedef for time_t.  The other half bumps the tint patch revision in buildrom
to take advantage of it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 21:29:48 +00:00
Carl-Daniel Hailfinger 967214d559 flashrom: Move the SPI #defines from spi.c to spi.h
This patch has no code changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 14:58:23 +00:00
Carl-Daniel Hailfinger a2e7c48d38 Change the SPI parts of flashrom to prepare for a merge of
ICH9 SPI support. In theory, this patch has no behaviour changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 14:01:22 +00:00
Carl-Daniel Hailfinger 6d3fdf9b62 MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OK
by Harald Gutmann.
SST39VF040 has been confirmed to probe OK by misi e.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12 21:19:53 +00:00
Carl-Daniel Hailfinger c95f2a737a Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF
series has the same IDs.
Add short AMIC vendor ID to flashrom.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12 14:25:31 +00:00
Uwe Hermann d0e687ac39 Fix the build when serial console support is disabled (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11 16:13:24 +00:00
Uwe Hermann 134aaaec50 Quickfix to repair 'make clean; make menuconfig' (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11 15:51:31 +00:00
Carl-Daniel Hailfinger cd0b5631de Improve flashrom SPI abstraction, second step.
This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.

The third step would be calling SPI controller functions via a function
pointer.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10 23:40:51 +00:00
Peter Stuge 31ab0314d1 flashrom: Rename generic_spi_*() functions to spi_*()
This is a very early step toward cleaning up SPI code in flashrom.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10 23:07:52 +00:00
Jordan Crouse fa36f5048f coreboot-v2: Disable second serial port on Norwich
There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-09 15:32:46 +00:00
Uwe Hermann bbd337e364 Add support for dumping ITE IT8718F EC registers (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 14:37:12 +00:00
Uwe Hermann 8cb2458005 Don't split up register list in two blocks, otherwise "Register dump:"
will be printed twice in the output (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 13:50:23 +00:00
Claus Gindhart 15da8ed98b flashrom: Probe for up to 3 flash chips.
Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
For this reason some boards have multiple chips of different technologies
onboard. This patch makes flashrom probe for up to 3 chips and if more than
one chip is found flashrom exits, asking the user to specify -c.

[root@localhost src]# ./flashrom
...
Multiple flash chips were detected: SST49LF008A M25P16@ICH9
Please specify which chip to use with the -c <chipname> option.
[root@localhost src]# 

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Claus Gindhart <claus.gindhart@kontron.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 00:31:44 +00:00
Ed Swierk 83a965d2ef Implement GPIO configuration routines for the Intel 3100 southbridge,
allowing you to specify per-mainboard GPIO settings.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 21:57:12 +00:00
Jordan Crouse aa6e378c4e coreinfo: Add a module for browsing the boot LAR
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 20:43:15 +00:00
Jordan Crouse 681ec27e2c libpayload: Add LAR walking support
Add suport for walking LARs.  These try to emulate the f*
functions from POSIX, though they are obviously different
in their behavior.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 20:34:02 +00:00
Ed Swierk 35993a231e Fix a typo in lbtdump output (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 19:21:18 +00:00
Jordan Crouse 193378698e coreinfo: Show the current time and date in the menu
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:15:31 +00:00
Jordan Crouse de7fc55920 We were in the risk of running out of space in the option menu at
the bottom of the screen - this turns the function keys into
categories and then list specific items as part of the category.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:03:16 +00:00
Jordan Crouse 7ce2666249 The previous commit had more in it then I wanted - so I am reverting
this and re-commiting so that the history and comments are correct.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:00:55 +00:00
Jordan Crouse 646ee3eae9 coreinfo: Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFO
rdtsc.h shouldn't be included unless we really need it (and use it).
Trivial.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 21:32:52 +00:00
Marc Jones 9d9518ff54 cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 16:56:47 +00:00
Myles Watson c314b2fcec This patch changes Config-lab.lb for qemu to use lzma like the other targets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 15:17:43 +00:00
Aaron Lwe 2342f8b343 This patch adds pc keyboard init function call for qemu in v2 since some payloads assume
Coreboot initializes it.  Coreboot v3 already does it.

Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 15:02:22 +00:00
Jonathan A. Kollasch 4f9141758e Fix various issues on MSI MS-7135 board.
- W83627THF is strapped to 0x4e, not 0x2e
 - there's no device 9 on PCI-E x1 bus, it should be device 0
 - add mptable entries for AGR slot, based on info in user manual
 - enable floppy drive controller so that some legacy VGA ROMs will work

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 13:26:32 +00:00
Ward Vandewege 33c57f8403 This patch changes the payload path for Config.lb; this board is supported by
buildrom and this bit was forgotten during r3092.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-05 20:50:58 +00:00
Peter Stuge 4934fc03cb flashrom: Add a tested bitmap field to the flash chip table.
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.

All chips are TEST_UNTESTED for now.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-03 04:34:37 +00:00
Ed Swierk a9a5f49d8f By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
for both serial ports, making it challenging to use COM2 for the early
console.

Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30 18:29:35 +00:00
Bari Ari e21f836e4e flashrom: Enable ROM decode range to 1MB for vt8237r
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-29 13:46:38 +00:00
Claus Gindhart b19973eb8b The generic jedec.c does not work for the ST M50FLW flash
devices, because they need an unlock command first.
For this reason, ST M50FLW support is moved to a
new HW support module, because any change in jedec.c
would bear the risk to cause problems with the already
supported devices.

It's already tested with ST M50FLW080A; the other
chips of this family i dont have available, so i couldnt
test it.

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 17:51:09 +00:00
Peter Stuge 26e08b5abe flashrom: Handle NULL probe, erase and write function pointers in the
flashchips table. The read pointer was already checked properly.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 14:47:30 +00:00
Jordan Crouse e2271430c5 libpayload: Add gettimeofday() and friends
Add a gettimeofday() implementation - it works pretty well, but it
drifts a little bit so its not very suitable for keeping time.  It
works best to track changes in time over small periods of time.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:11:02 +00:00
Jordan Crouse d772e1e7fe libpayload: Fix a small but aggressive bug in printf()
This was causing the returned counter value to be one more then it
should be when printing a single character.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:10:23 +00:00
Jordan Crouse 63f181f97c libpayload: Enable keyboard translation so that we can use scancode set 1
The qemu keyboard controller defaults to using scancode set 2, we use set 1.
Turn on the translate mode in the keyboard controller to force the issue.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:09:39 +00:00
Jordan Crouse 24a0404759 libpayload: Fix malloc allocation
Apparently the previous version worked on luck.  Fix the allocation
and add parens to better guide the compiler.  Also, halt() if 
the heap is poisoned (like by an overrun).  Finally, fix calloc()
so that it actually works.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:08:47 +00:00
Jordan Crouse c781584936 libpayload: Add the null terminator to the end of the duplicated string
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:07:39 +00:00
Marc Jones 20ce60c9aa Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb.
The FAM10 code takes up more space in the uncompressed "ROMCC" portion
of coreboot. Also, It is still growing as features are added.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 22:56:57 +00:00
Marc Jones 65e08040f9 Remove inline from FAM10 CPU initialization functions.
This doesn't save any space for me but it is the right thing to allow GCC to
optimize.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 21:34:25 +00:00
Aaron Lwe 7ca3ec2e5c Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 02:02:33 +00:00