This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of
a write operation since the other bits in the register are reserved.
Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN
using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable`
in the devicetree. This is required to get I2S_Wake event on headset jack
plug/unplug when using CODEC_GPI pad.
BUG=b:146317284,b:161328042
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 56da63c3dc removed overriding that
field in the FADT.
Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the code and data in psp_verstage is ~59K. Adding the code
to save vbnv to the SPI rom increases that to 66K.
Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to.
BUG=b:161366241
TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This
function call in picasso does not do anything and hence is being dropped.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.
BUG=b:158695393
TEST=Mandolin still boots.
Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This provides the functionality to provide the GPE to the pci_xhci
driver.
BUG=b:154756391, b:160651028
TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and
verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is now a generic xhci driver we can use to generate the xHCI ACPI
nodes.
BUG=b:154756391
TEST=Boot trembyle and look at ACPI table
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Data fabric devices are PCI devices which support PCI configuration
space but do not require any MMIO/IO resources. This change adds a PCI
driver for the data fabric devices which only provides device
operations for adding node to SSDT and returning the ACPI name for the
device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a driver pcie_gpp.c which provides device_operations
for external and internal PCIe GPP bridges. These device operations
include standard PCI bridge operations as well as operations for
generating ACPI node for the device and returning appropriate ACPI
name for it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When entering S3, zork shuts down the i2c controllers to save power.
On resume, we need to re-enable i2c before accessing them, so we need
to map the AOAC registers in verstage.
BUG=b:160834101
TEST=psp_verstage works after resume.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it
there. The soc/amd/* code itself uses the bit definition when accessing
HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition.
Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR,
since that bit isn't in that MSR.
TEST=Checked the code and the corresponding BKDG/PPR.
Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The kernel requires the display oprom is loaded and ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:160560510
TEST=Boot Trembyle in developer mode and normal mode
Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Remove I2C4 since it is a slave device used for USB-C mux control
and should not be included with the other master devices.
BUG=b:160624619 b:160292546
TEST=EC can communicate with AP mux I2C4 slave
Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing. Add dummy spinlock code as the spinlocks
aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the APOB size & base generation the same as all the other command
line arguments to amdfwtool.
BUG=None
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id78383d87bc98dd2c859c75585266411c226f950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This was specifically needed for vboot with psp_verstage, but adding
it to always be built into bootblock if needed like memcpy & memset
makes sense.
TEST=Build & boot trembyle
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Check for the workbuf in bootblock if psp_verstage is being used.
BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can't set the SMI or SCI flags in psp verstage, so skip them.
TEST=Build
BUG=b:154142138
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings. When these are moved to the RW-A & RW-B
regions, the packages need to be recreated for the new addresses.
TEST=Build & boot trembyle. See that we're booting from the correct
region.
BUG=b:158124527
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds the psp_verstage userspace application and the location of
the shared memory area to the amdfw binary tables.
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP. It does a minimal setup of hardware,
then runs verstage_main. It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.
BUG=b:158124527
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.
BUG=b:156315391
TEST=Build, verified the tuning value been applied on Trembyle.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The bootblock must be 16-bit aligned for it to boot.
BUG=b:159081993
TEST=Made sure trembyle still compiles.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Skip sending MboxBiosCmdSxInfo for sleep states other than S3. The
PSP only acts on S3 and ignores all others. As a result, the command
register is not cleared upon return and coreboot reports a timeout.
BUG=b:153622879
TEST=Use halt from command line, verify command skipped.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
eSPI interrupts are active level high. The eSPI polarity register
in the chipset inverts incoming signals if the corresonding bit
is 0 in the register. Therefore, all active high (edge or level)
virtual wire interrupts need to ensure they are not inverted.
And really the sender of the interrupts should be conforming to the
the eSPI spec. As such inverting any signals should not be necessary,
but this register in the chipset allows for fixing up those misbehaviors.
BUG=b:157984427
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds support in ACP device driver to generate I2S machine
device (AMDI5682) in SSDT. It expects mainboard to provide chip config
`dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the
device.
BUG=b:157603026
TEST=Verified that I2S machine device is correctly generated for
trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252557
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ACPI code was not masking off the correct bits for publishing
the SPI bar to the OS.
It resulted in a dmesg messagelike:
system 00:00: [mem 0xfec10002-0xfec11001] has been reserved
And /proc/iomem entry
fec10002-fec11001 : pnp 00:00
These addresses are wrong because they are including bits of a
register that are not a part of the address.
Moreover, the code does not publish the eSPI register area either.
The eSPI registers live at 0x10000 added to the SPI bar. Lastly,
both regions are less than a page so only report a page of usage
for each.
Stoney Ridge's SPI bar register defines the address as 31:6 while
Picasso's SPI bar register defines the address as 31:8. Use Picasso's
valid mask for both cases because no one is assigning addresses
that are aligned to less than 256 bytes.
With the fixes, dmesg reports:
system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved
system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved
And /proc/iomem indicates:
fec10000-fec10fff : pnp 00:00
fec20000-fec20fff : pnp 00:00
BUG=b:160290629
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42959
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change clears interrupt and wake status for a pad when
configuring it. This ensures that stale interrupts/wake notifications
are flushed out and do not cause spurious wakes in future suspends.
BUG=b:159944426
Change-Id: Ia4ebd975312a4136f1d0690d7af7372615e31f0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`flags` field of soc_amd_gpio structure is set only for SCI and SMI
configurations. This change adds a new helper macro
PAD_CFG_STRUCT_FLAGS that allows setting of all soc_amd_gpio members
including `flags` field. This can be used directly by PAD_SCI and
PAD_SMI. For all other pad configurations, PAD_CFG_STRUCT macro uses
PAD_CFG_STRUCT_FLAGS with flags set to 0. This allows dropping of
redundant parameter 0 for flags for all other pad configurations.
BUG=b:159944426
Change-Id: I835b62f5502375ffc4215548b51338a67546d699
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, for Stoneyridge and Picasso mainboards, pads that are
configured for SCI/SMI/WAKE need to have multiple entries in the
configuration table - one for PAD_GPI and other for the special
configuration that is required. This requires a very specific ordering
of pads within the table and is prone to errors because of conflicting
params provided to the different entries for the same pad. This also
does not work very well with the concept of override GPIOs where the
entry in base table is overridden with the first matched entry from
the override table.
This change updates the way GPIO configuration is handled for special
routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of
soc_amd_gpio structure in the macros performing these
configurations. Also, program_gpios() is updated to perform a write to
GPIO control register instead of read-modify-write. This is because
mainboard is expected to provide only a single configuration entry for
each pad within a given table. Thus, there is no need to preserve
earlier configuration.
Mainboards that were providing multiple entries for a single pad are
updated accordingly.
BUG=b:159944426
Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some codepaths want to set selected bits of a hardware register
to match those of a given variable in memory. Provide a helper
function for this purpose and use it in gpio_set(),
gpio_input_pulldown() and gpio_input_pullup().
This change also adds GPIO_PULL_MASK and updates GPIO_OUTPUT_MASK to
include all bits dealing with pull and output respectively.
Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
