This change adds mem_list_variant.txt that contains the list of
memory parts used by volteer and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Part: K4UBE3D4AA-MGCL
Byte# Current New Explanation
6 0xB5 0xB4 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
Part: H9HCNNNBKMMLXR-NEE
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: H9HCNNNFAMMLXR-NEE
Byte# Current New Explanation
4 0x15 0x16 As per datasheet, density is 16Gb per
logical channel. So value should be 0x16.
6 0xF9 0xB8 This device has 4 logical dies
instead of 8. Also, signal loading is
not used by MRC.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
20,21, 0x92,0x55, 0x12,0x29, As per datasheet, part supports CAS
22 0x00 0x15 latencies 6,10,16,22,26,32,36,40. So value
should be 0x12,0x29,0x15.
24 0x8C 0x96 taa is .468ns * CAS-40 which results
in byte 24 being 0x96 as per datasheet.
29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to
280ns in MTB units which is 0x08C0.
31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to
140ns in MTB units which is 0x04C0.
123 0x00 0xE2 Fine offset for taa. Expected value
is 0xE2 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: MT53E1G32D2NP-046 WT:A
Byte# Current New Explanation
4 0x15 0x16 As per datasheet, density is 16Gb per
logical channel. So value should be 0x16.
5 0x21 0x29 As per datasheet, this part has 17row
address bits and 10column address
bits. This results in 0x29.
6 0xB5 0x94 This device has 2 logical dies. Also,
MRC does not use signal loading.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
12 0x0A 0x02 As per datasheet, this is 1rank and
16-bit wide channel. So, value should
be 0x02.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to
380ns in MTB units which is 0x0BE0.
31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to
190ns in MTB units which is 0x05F0.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:147321551,b:155423877
Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change adds mem_list_variant.txt that contains the list of
memory parts used by halvor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: H9HKNNNCRMBVAR-NEH
Byte# Current New Explanation
4 0x16 0x15 As per datasheet, density is 8Gb per
logical channel. So value should be 0x15.
6 0xB9 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00. 2 channels 2
dies. Hence, 0x94
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to
280ns in MTB units which is 0x08C0.
31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to
140ns in MTB units which is 0x0460.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: MT53E1G64D4SQ-046 WT:A
Byte# Current New Explanation
5 0x21 0x29 As per datasheet, this part has 17row
address bits and 10column address
bits. This results in 0x29.
6 0xB9 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00. 2 channels,
2 dies. Hence, 0x94.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:147321551,b:155423877
Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_list_variant.txt that contains the list of
memory parts used by malefor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Bits 1:0 set to 0.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:155239397,b:147321551
Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_list_variant.txt that contains the list of
memory parts used by ripto and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Bits 1:0 set to 0.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:155239397,b:147321551
Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that
can be used with JSL-based mainboards.
Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go
Mainboards can use the SPD files from SoC directly when creating
SPD binary to add to CBFS.
Change-Id: Ic52506b809c66b9f7cf25a100a959d85c67addf2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41876
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with TGL-based mainboards.
Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go
Mainboards can use the SPD files from SoC directly when creating SPD
binary to add to CBFS.
BUG=b:147321551,b:155239397
Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds a JSON file (`global_lp4x_mem_parts.json.txt`)
containing global list of LP4x memory parts to live along with the spd
tools since the part information is not really any SoC or mainboard
dependent and comes directly from the part datasheet. It can be shared
by mainboards based on different platforms supported by the tools.
BUG=b:155239397,b:147321551
Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.
In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for LPDDR4x
memory used in memory down configurations on Intel Tiger Lake (TGL)
and Jasper Lake (JSL) based platforms. These tools generate SPDs
following JESD209-4C specification and Intel recommendations (doc
Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
part list provided by the mainboard in JSON format. Additionally,
generates a SPD manifest file (in CSV format) with information about
what memory part from the global list uses which of the generated
SPD files.
* gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x
memory parts used by the board. Takes as input list of memory parts
used by the board (with one memory part on each line) and the SPD
manifest file generated by gen_spd.go. Generates Makefile.inc for
integrating the generated SPD files in the coreboot build.
BUG=b:155239397,b:147321551
Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This fixes a logic bug in how timeouts are reported back. In the
timeout case, the original code would return -1 instead of 0. All call
sites expect a return value of 0 as the timeout indicator.
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Advertising SMI triggers in FADT is only valid if we exit with
SMI installed. There has been some experiments to delay SMM
installation to OS, yet there are new platforms that allow some
configuration access only to be done inside SMM.
Splitting static HAVE_SMI_HANDLER variable helps to manage cases
where SMM might be both installed and cleared prior to entering
payload.
Change-Id: Iad92c4a180524e15199633693446a087787ad3a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If running on older (like before 2.4.0) version of QEMU there is
no SMI support, so never advertise SMI in FADT for the emulation.
Behaviour if ACPI daemon tries to raise SMI under these conditions
is unknown.
Change-Id: I170058793798648c6713de1530d89ec2ac53e39a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Ia61e50fb49719e9e18e81a27f355cdbd755a3f40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a hook so that a payload can optionally perform USB service
functions in conjunction with regular USB port status polling. In
particular, this allows depthcharge to control the state of an
external USB mux. Some SoCs like Tiger Lake have a USB mux for Type-C
ports that must be kept in sync with the state of the port as reported
by the TCPC. This can be achieved by hooking into the poll routine to
refresh the state of the USB mux.
BUG=b:149883933
TEST=booted into recovery from Type-C flash drive on volteer
Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
CB:41384 (SHA dbcf7b1621) added some new
functionality to devicetree files ("hidden PCI devices"). It's a decent
enough semantic change that it should be added to the release notes for
the 4.13 release.
Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We decided to store the FSG on eMMC instead of SPI flash, so we don't
need this region anymore. Getting rid of it allows us to put more space
into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining
amount to keep the FMAP alignment reasonable.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but
turned out to be correct.
Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a helper function set_mmio_dev_ops() in chip.c which
is used for setting the dev->ops for MMIO devices based on the
comparison of MMIO address in device tree to the pre-defined base
addresses in iomap.h.
Call to i2c_acpi_name() is replaced with set_mmio_dev_ops and scope of
i2c_acpi_name is restricted to i2c.c since it is not required to be
exposed out of that file.
Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Drop functions that are not being used.
Change-Id: If406601f3bb7a98a621c1339b2f3413a43b8cc9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There have been changes to the way device properties are supported
in Linux[1] and Windows[2] which add flexibilty:
- non-standard UUIDs can be used instead of only ACPI_DP_UUID
- support for multiple different packages within the _DSD that
associate different properties with unique UUIDs.
To handle this I extracted the part that does the write of UUID and
properties to a separate function and defined a new PACKAGE type
which has the custom UUID as a name and can be used the same way that
child properties are today.
For example a PCIe root port for a USB4 port has a standard property
indicating the USB4 reference, and then two custom properties which
are defined for different attributes.
Example code:
/* Create property table */
acpi_dp *dsd = acpi_dp_new_table("_DSD");
acpi_dp_add_reference(dsd, "usb4-port", usb4_path);
/* Add package for hotplug */
acpi_dp *pkg = acpi_dp_new_table("6211e2c0-58a3-4af3-90e1-927a4e0c55a4");
acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1);
acpi_dp_add_package(dsd, pkg);
/* Add package for external port info */
pkg = acpi_dp_new_table("efcc06cc-73ac-4bc3-bff0-76143807c389");
acpi_dp_add_integer(pkg, "ExternalFacingPort", 1);
acpi_dp_add_package(dsd, pkg);
/* Write all properties */
acpi_dp_write(dsd);
Resulting ACPI:
Scope (\_SB.PCI0.TRP0)
{
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package ()
{
Package () { "usb4-port", \_SB.PCI0.TDM0.RHUB.PRTA }
},
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package ()
{
Package () { "HotPlugSupportInD3", One }
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package ()
{
Package () { "ExternalFacingPort", One },
}
})
}
[1] https://patchwork.kernel.org/patch/10599675/
[2] https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
Change-Id: I75f47825bf4ffc5e9e92af2c45790d1b5945576e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create the voxel variant of the volteer reference board
BUG=b:157879197
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOXEL
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8ba5412be211730db84675927c500238cb20ff3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
We previously confirmed [1] that bootblock will grow beyond current
8KiB size if console is enabled. Automatically change to 16KiB if user
enabled it in menuconfig.
[1] https://review.coreboot.org/c/coreboot/+/36775
Change-Id: Ic9988c77cf9677167a382aa4dc7dcfa2bc4cbe02
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41460
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If AMD_PUBKEY_FILE contains an absolute path the resulting path is
incorrect since it contains $(top).
BUG=b:147042464
TEST=Build trembyle with absolute and relative path.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add PCIe enumeration and resource assignment/allocation.
Xeon-SP processor family has split IIO design, where PCIe domain 0 is
split into multiple stacks. Each stack has its own resource ranges (eg.
IO resource, mem32 resource, mem64 resource). The stack itself is not
PCIe device, it does not have config space to be probed/programmed.
The stack is programmed by FSP. coreboot needs to take into account of
stack when doing PCIe enumeration and resource allocation.
Current coreboot PCIe resource allocator does not support the concept of
split IIO stack, thus entire support is done locally in this patch.
In near future, improvements will be done, first generalize for xeon-sp,
then generalize for coreboot PCIe device code.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
offsets for ACPI_PM are incorrectly configured for picasso SoC.
Especially incorrect ACPI_PM_TMR_BLK makes kernel to spend 10 sec for
trying to testing it on wrong address.
Fix them to correct offset with hack for GPE0_BLK.
BUG=b:147044624
TEST=build and boot on trembyle; PM Timer error is gone
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6adf71479c30f5b6751a21edc4bfa311ddbef5ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
BUG=chromium:1088209
TEST=emerge coreboot-utils (with patches to the ebuild) works
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I25d237d048e417f4e412583031905ecf3614c431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The default HID was removed by a1c82c5ebe. We need to explicitly
specify it.
BUG=b:154756391
TEST=No longer see ERROR: _HID required message in console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the device is missing the HID, the code would previously leave an
open scope and device on the stack.
BUG=b:154756391
TEST=Verify stack ACPI stack does not exceed limit on Trembyle.
Fixes: a1c82c5ebe ("drivers/generic/max98357a: Allow custom _HID from config")
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I798ed08ef0a0575def12937a66a7ce99f743e60d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These devices never show on the PCI domain.
Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for google/link.
Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for
google/beltino.
Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Furquan Shaikh