Commit Graph

28786 Commits

Author SHA1 Message Date
Jiaxin Yu 30bc9f415d google/kukui: Support sound in boot process
Configure and enable GPIO for speaker amp max98357a.

BUG=b:117254418
TEST=Build pass and verified on kukui p1 board
BRANCH=None

Change-Id: I97655702dff402245326d2eff71fae0e336df9f5
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-07 16:00:31 +00:00
Nico Huber 3c0d23b6ab intel/fsp1_1: Drop remnants of `pei_data`
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.

Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:59:10 +00:00
Nico Huber 0ebdf2ac75 mb/purism/librem_skl: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
never consumed anywhere again. So just merge the used code into
`romstage.c` where it's effectively used.

Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:58:39 +00:00
Nico Huber feb50f15cc mb/google/glados: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:58:32 +00:00
Nico Huber 85f0b051ba mb/google/cyan: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

The provided solution locates the SPD data in CBFS again to fill SMBIOS
tables. This is not perfect. OTOH, this code isn't mainboard specific
and doesn't belong here anyway.

Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:58:05 +00:00
Nico Huber ec562161cd soc/intel/bsw: Move memory init values into `romstage.h`
`chip.h` is usually used as devicetree interface.

Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 15:57:51 +00:00
Nico Huber f98f8ebb8c mb/intel/saddlebrook: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:57:15 +00:00
Nico Huber 9b5b9e46b9 mb/intel/kunimitsu: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

Change-Id: Ibc013ccea9f83ef29f22fe2da4c0d12096308636
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:57:05 +00:00
Nico Huber 66318aad07 intel/fsp1_1: Move MRC cache pointers into `romstage_params`
These are part of a common concept and not SoC specific.

Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-07 15:55:50 +00:00
Patrick Georgi 99e836c843 Revert "Makefile.inc: Enable -Wtype-limits"
This reverts commit c4ab50cdde.

Reason for revert:
vboot recently was changed so that -Wtype-limits fails, and that
was just brought upstream. Since vboot internals are more likely
to be used elsewhere while -Wtype-limits is less critical, revert
this until vboot is resolved, then bring -Wtype-limits back again.

Change-Id: I9cce10462b9e57189513fa49e11fd27ebe35ba51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32670
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 15:53:54 +00:00
Nico Huber 16895c529c intel/fsp1_1: Drop `boot_mode` from `pei_data`
It was only used locally.

Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-07 15:53:26 +00:00
Nico Huber a842d3ee6a intel/fsp1_1: Drop unused, weak raminit()
Change-Id: I5d155df1d589fc8d7462f46e87275bd6efae0a7f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-07 15:52:36 +00:00
Elyes HAOUAS 66b35bad88 mb/lenovo/x60: Use system_reset()
Change-Id: I4515d8d14629741f3bf49e9459d7d57c18d321ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07 15:52:07 +00:00
Elyes HAOUAS 1bc7b6e135 {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function
Use already defined system_reset() and full_reset() functions.

Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07 15:52:01 +00:00
Evgeny Zinoviev ba092a9ab6 mb/apple/macbookair4_2: Correct internal video port selection
The MacBook Air 4,2 uses eDP, according to the schematics.

Change-Id: Ifc98eab343fd89b8512e92e01fddf34ef8447d5f
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 15:51:30 +00:00
Joel Kitching 0de835d52e Update vboot submodule to upstream master
Updating from commit id 304aa429:
2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags)

to commit id e7edff66:
2019-05-03 07:02:32 -0700 - (vboot: implement DISPLAY_INIT context and SD flag)

This brings in 45 new commits.

Change-Id: I7493e43bddc553f9724de46130ccb4cb44e18573
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07 07:42:59 +00:00
Eric Lai 0c0a9810c7 mb/google/sarien: Turn off camera power when s0ix
Turn off camera power when s0ix for power saving.

BUG=b:129177593
TEST= measure camera power comsumption is 0mV under s0ix

Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-06 17:31:11 +00:00
Eric Lai 8c0acc5515 mb/google/sarien: Fine tune SD card D3 cold timing
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.

BUG=b:131876963
TEST=boot up and check SD card functional

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-06 15:59:55 +00:00
Joel Kitching 1a6b5c23a1 vboot: remove use of GoogleBinaryBlockHeader
Remove use of deprecated GoogleBinaryBlockHeader struct, and
replace with vb2_gbb_header.

BUG=b:124141368, chromium:954774
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-06 12:40:31 +00:00
Elyes HAOUAS 45b824d694 src: Remove unused include <halt.h>
Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-06 10:39:01 +00:00
Felix Singer 0a7543db2d inteltool: Add Sunrise Point-LP Skylake PCH IDs
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.

This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.

Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)

Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:38:49 +00:00
Bluemax b4951c92a1 Documentation: Add MSI MS-7707
Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:37:04 +00:00
Patrick Rudolph a06fa32daf arch/x86: Remove unused file
The file is no longer used by any code. Remove it.

Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-06 10:36:40 +00:00
Matthew Garrett 78b58a4996 drivers/intel/fsp2_0: Fix fsp post-init validation
Part of this checks whether tolum_base and cbmem_top are the same - however,
cbmem_top hasn't been initialised at the point where this call occurs.
Change the ordering to fix that.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-06 10:35:25 +00:00
Karthikeyan Ramasubramanian 6629b4bbf8 soc/intel/apollolake: Reset GPI IS & IE registers at ramstage
Reset GPI Interrupt status and enable registers from ramstage instead of
bootblock so that it applies to devices in field.

BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:34:52 +00:00
Eric Lai 7f1e9dbf3a soc/intel/cannonlake/acpi: Add board level s0ix call back
Add board level s0ix call back. Since some driver doesn't
care _ON/_OFF method. Add a control method for s0ix usage.

BUG=b:129177593
TEST=NA

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-06 10:34:35 +00:00
Felix Singer e59ae107c2 soc/apollolake: Add ramstage hook
A hook for romstage is already existing but not for ramstage.

It's very useful for debugging as it allows to run code
for testing purposes by the mainboard. Also, it allows to
run configuration code or configure FSP options, which
don't have a devicetree option.

Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:34:10 +00:00
Marshall Dawson 1bc04e3c3e soc/amd/stoneyridge: Correct bugs in lpc.c
Remove the bridge enable step of accessing D14F0x64.  This method for
enabling the bridge appears to be last present in the SB700 device.
Beginning in the SB800 (and all FCH, SoC devices), the enable is in
PMxEC[0].  Since the bridge is enabled in bootblock to allow port 80h,
there is no need to maintain it in ramstage.

Correct the device used for misc. configuration of the LPC bridge.
The #defined value removed is 14.0 but the settings are in 14.3.

TEST=Boot Grunt, check console and dmesg for errors and warnings
BUG=b:131862871

Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-05-06 10:33:03 +00:00
Marshall Dawson e09caf6428 soc/amd/stoneyridge: Move acpi_fill_mcfg to northbridge
Relocate the function to the more appropriate file.

Change-Id: I92a3e8d0461ae228f6c01567db159e2458de5f6b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-06 10:32:42 +00:00
Julius Werner c4ab50cdde Makefile.inc: Enable -Wtype-limits
This patch enables -Wtype-limits for the whole repository, which
disallows checking for a condition that must be always true or always
false based on type width (e.g. checking whether an unsigned variable is
negative or whether a 32-bit integer is larger than 4G). This helps
avoid easy to make and hard to find (because they often only affect
error paths) mistakes like

 size_t size = fmap_read_area(...);
 if (size < 0)
   die("If only the compiler could've told me to use ssize_t instead");

Change-Id: I19edabfd092d09dad720e3fc47b44838163bfe25
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32536
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:32:24 +00:00
Julius Werner 7c712bbb6c Fix code that would trip -Wtype-limits
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.

Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:32:15 +00:00
Julius Werner 9d3fa7a229 spd_bin: Do not depend CONFIG_DIMM_MAX on CONFIG_GENERIC_SPD_BIN
I can't claim that I really understand what this code does, but it looks
like there are platforms that use code from lib/spd_bin.c without
enabling CONFIG_GENERIC_SPD_BIN. Some functions in that file contain
references to CONFIG_DIMM_MAX, so that option probably shouldn't depend
on CONFIG_GENERIC_SPD_BIN.

Change-Id: I041c52b6bd255e9a9920e5a101165ba5fc5fa6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32548
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:31:38 +00:00
Matt DeVillier 6a4a026e13 purism/librem_skl: remove 13v3 target, clean up Kconfig
Remove the Librem 13v3 as a separate board; instead build a
single firmware image for the 13 v2/v3 boards.

Clean up Kconfig options:
- remove entries for 13v3 board
- fold entries into a single line where possible
- remove redundant MAINBOARD_VERSION option (will default to 1.0)
- remove unused microcode length/location (only needed for FSP CAR)

Test: build/boot Librem 13 v2/v3 boards with same image

Change-Id: Ic09b8ec5c576f4c4c48ef30ee3f60a4c2c286cd3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-06 10:30:27 +00:00
Elyes HAOUAS 32f48a2d56 mb/google: Remove unused 'include <smbios.h>'
Change-Id: Ib96c317391745fa5afea785e3c7441124b3fc252
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-06 10:30:05 +00:00
Jacob Garber fb0fa7643e sb/amd/rs780: Use 32 bit variable to avoid truncation
The {read,write}_index functions expect a 32 bit value, as
do the bitwise operations.

Found-by: Coverity Scan #1229584
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Idc2bc46c899d5a4e8b089644dca076a88d97dd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-06 10:29:28 +00:00
Frans Hendriks 5471be69b9 soc/intel/braswell/Makefile.inc: Remove commented-out line
cpu_microcode_bins is commented out.
Remove this line.

BUG=NA
TEST=Portwell PQ7-M107

Change-Id: Ic398d232bea84a765fce940ef876916a873e561f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32510
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:29:13 +00:00
Marius Genheimer 4998becda3 soc/skylake: Add missing PCH IDs
Added IDs for:
- H170
- Z170
- Q170
- Q150
- B150

Used documents:
- 332690-005EN

Tested on Gigabyte GA-Z170N-WIFI

Change-Id: If20a2b764afa02785a97948893dbc5b5f60aff60
Signed-off-by: Marius Genheimer <mail@f0wl.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32517
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:29:02 +00:00
Patrick Rudolph 72a9091a0e sb/intel/bd82x6x: Use common/rcba.h
Make use of:
* southbridge/intel/common/rcba.h
* southbridge/intel/common/pmbase.c
* defines in pch.h

Get rid of dependency to DEFAULT_RCBA.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32066
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:28:42 +00:00
Tristan Shieh 0dd6b55a7e google/kukui: Raise the CPU frequency
Run CPU at the highest freqency (1989MHz) to speed up the boot time.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32466
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:28:09 +00:00
Tristan Shieh b75f493ed7 mediatek/mt8183: Wait 200us for voltages to settle
When we increase voltages, it takes 200us for voltages to stablize.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: I5f32035693b6084dbe763411c612ae5d1f7c9e48
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-06 10:27:53 +00:00
Tim Wawrzynczak 3fe7c44d50 mainboard/google/hatch: Enable PEN_EJECT_L as wake & notify source.
Updated GPP_A8 to be a GPI and SCI source, to support both wake and
notifications.

BUG=b:128941098
BRANCH=none
TEST=Compiles, simulated pen eject with PCH_INT_L signal.  Both evtest
and waking from s0ix confirm this works.  The output of /proc/interrupts
confirms the correct interrupt is triggered.

Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-06 10:27:28 +00:00
Tim Wawrzynczak 939440c48b soc/intel/cannonlake: Add GPIO dual-route support.
Select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT in Kconfig

BUG=none
BRANCH=none
TEST=compiles

Change-Id: If5f59ea50c13bd1f279637e281468e6d0312dbab
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:27:17 +00:00
Tim Wawrzynczak 95f8884c95 soc/intel/common: Add new PAD_CFG macro.
Added macro named PAD_CFG_GPI_GPIO_DRIVER_SCI, for pads that need to be
configured as GPI, GPIO Driver mode, and SCI interrupt.

Also remove PAD_IRQ_CFG_DUAL_ROUTE macro (subsumed by
PAD_CFG_GPI_IRQ_WAKE).

BUG=none
BRANCH=none
TEST=Compiles

Change-Id: I0332c64e2fa62ce29c772444606adbfdf9c9afc4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32485
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:27:07 +00:00
Frans Hendriks 683e77e479 drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80
Cosmetic change to reduce line length to 80 max.

BUG=NA
TEST=Build Portwell PQ7-M107

Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:26:50 +00:00
Kyösti Mälkki 85b2ed5438 soc/amd/common: Introduce module_dispatch()
This change removes all the separate entrypoint dispatch
functions as they all share the same pattern.

Furthermore, none of the function definitions under vendorcode
binaryPI/AGESA.c file have proper declarations, the ones compiler
picks up from AGESA.h are for the internal implementations and
with sanely organized headerfiles would not be exposed outside
the build of AGESA at all.

Change-Id: I0b72badc007565740c93b58743cfd048e8b42775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31485
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:26:25 +00:00
Frans Hendriks 43fc38943d mainboard/intel/strago/acpi: Serialize _CRS method
IASL reports warning 'Control Method should be made Serialized'.
Change _CRS method to Serialized.

BUG=N/A
TEST=Build Intel Strago

Change-Id: I63a7e1caab19360a9a5831458311d5a83fdf52d1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:26:11 +00:00
Werner Zeh 42065f8f94 mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
Due to PCB limitations the SD-Card interface is not able to operate
with the highest frequency reliably. The OS driver will switch to
the highest mode if a SD-Card is attached which supports this high
frequency mode. In order to work around this PCB limitation disable the
high frequency modes in the controller capabilities (SDR104 and HS400
mode) and leave SDR50 and DDR50 enabled.

Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 04:35:08 +00:00
Elyes HAOUAS 29a1a0857a mb/msi/ms7707: Remove MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID}
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed.

Change-Id: I70ef22aac165a19663749f76449907482b761316
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-05 10:47:58 +00:00
Matt DeVillier 73c312fce5 src/Kconfig: remove duplicate entry for drivers/fsp1_0/Kconfig
The entry for drivers/intel/fsp1_0/Kconfig was added under the
chipset menu before addtional FSP versions were added, and the
drivers/*/*/Kconfig entry added to support them. This results
in the fsp1_0 Kconfig items being duplicated in the Chipset and
Generic Drivers menus.

Remove the chipset entry since it's no longer needed.

Test: select FSP 1.0 mainboard (e.g. intel/minnowmax) in menuconfig,
observe FSP 1.0 Kconfig entries listed only under Generic Drivers menu.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: If1e78fb9259b1a46d308db829881eb3b3d17cf40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32565
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-04 20:12:44 +00:00
Frans Hendriks e6bf51fb22 {soc, southbridge} : Correct typo in comment
BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03 22:39:14 +00:00