Commit Graph

44873 Commits

Author SHA1 Message Date
Simon Glass 2e6c9d6488 payloads/U-Boot: Do a shallow clone
We don't need all the git history. Speed up the build by doing a shallow
clone.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: If31c9dd158aa23f242e4fd145449ef7502fb1ab1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:04:47 +00:00
Simon Glass ed533f7077 payloads/U-Boot: Use the correct output binary
The u-boot.bin file should be used, rather than u-boot-dtb.bin

While they are often the same, the -dtb version is really just for
legacy use now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I5558ed94c7dd6cc57ceb835fe367bfa050ad2150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:04:36 +00:00
Simon Glass 03f0fa1822 payloads/U-Boot: Tidy up the U-Boot build
This doesn't work at present, merely printing an error when U-Boot is
selected as a payload. This is because it adds a file into the U-Boot
tree which makes U-Boot's build system think that the tree is unclean.

Update the rules to put the tag file outside the source tree. Use an
out-of-tree build for U-Boot to avoid changing the source tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I24d6545b54f97afeefaca3ffed79eec2e7afacb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:04:06 +00:00
Malik_Hsu 4298e13868 mb/google/brya/variants/primus: add fw config probe for speaker amp
Added fw config probe for MX98360A.

BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I2452b752ce58a5d0f1008cf187fb79ace6c4285f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 19:43:19 +00:00
Curtis Chen 0c54461cf9 soc/intel/alderlake: Add ADLP 4+4+2 power configurations
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).

BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 19:43:00 +00:00
Felix Held d560ad6e7a soc/amd/*/data_fabric: use DF_ prefix for bit and shift defines
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE
clarifies the scope of those definitions. For consistency also add this
prefix to MMIO_DST_FABRIC_ID_SHIFT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 18:46:16 +00:00
Felix Held 2f5cb2e355 soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specific
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register
is bit 12, but that has changed to bit 16 in Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I64c06b84e2c0737b259077e7932f418306638e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 18:46:11 +00:00
Felix Held f80f32b0e5 soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definition
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change
the name of the define to FCH_AOAC_REF_CLK_OK_STATE.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 18:45:53 +00:00
Felix Held 23d03e912a soc/amd/common/block/include/gpio_defs: add missing de-glitching defines
There were only definitions for removing low, high or both glitches, but
not to not remove glitches, so add this too for completeness.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I650f7754546935539339c02bb6a94bb3f855d4ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 18:44:47 +00:00
Felix Held 29b7f1459d soc/amd/common/block/include/gpio_defs: rework de-glitching defines
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 18:44:41 +00:00
Felix Held 18456169e6 soc/amd/common/block/include/gpio_defs: use tabs for indentation
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibf7482d20c6d27b2314ec8a31c349eb90c8a8feb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 18:44:36 +00:00
John Su 2cb8ed1128 mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter
The DPTF parameters were verified by the thermal team.

BUG=b:207463762
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 13:31:19 +00:00
Angel Pons ebf62d6aff commonlib/cbmem_id.h: Add names for some IDs
Some IDs don't have an associated name. Add them.

Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59617
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-25 11:13:41 +00:00
Angel Pons 5484a956b8 commonlib/cbmem_id.h: Fix typo in macro name
Rename `CMBMEM_ID_ACPI_HEST` to `CBMEM_ID_ACPI_HEST`.

Change-Id: I3e680244c9573f566b51298462c324e062ab4657
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59616
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-25 11:13:28 +00:00
Felix Held b2c2b92a6d soc/amd/common/block/gpio: drop unused gpio_get_address
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b47324af368f81288e9e9be65fe0f1ae2fa3697
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:09:17 +00:00
Felix Held 3215e004e4 soc/amd/common/acpi/gpio_bank_lib: drop unused methods
Those methods were only in the non-common Stoneyridge GPIO ACPI code
that got dropped, so drop those unused methods too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:09:05 +00:00
Felix Held 68aca73cfd soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUT
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idf00879701b223ecaca74aef2a51a1b86d2c6ce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:08:51 +00:00
Felix Held 0bc4684f89 soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO
Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so
we can use the common AMD SoC GPIO ACPI code.

TEST=none

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:08:36 +00:00
Felix Held a7190ef2ec soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs
De-duplicate the definitions for the pin status bit and use this new
definition in both the C and the ACPI code.

TEST=Timeless build results in identical image for amd/mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:08:12 +00:00
Felix Held baa72db1b2 soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs
The GPIO_WAKE_* definitions are the ones that are used in the code, so
drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move
the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were
before this patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622673cc72107908b525a65212061062f32e13dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:07:55 +00:00
Felix Held e2f30b4e56 soc/amd/common/block/include/gpio_defs: use bit definitions for masks
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK,
GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code
so use those instead of magic numbers.

TEST=Timeless build results in identical image for amd/mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:07:36 +00:00
Felix Held 61ac508712 soc/amd/common/block/include/gpio_defs: remove unneeded line break
The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and
GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded
line breaks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:07:19 +00:00
Felix Held c194f75bb5 soc/amd/common/block/include/gpio_defs: drop 8k pullup define
The corresponding bit is marked as reserved in the following versions of
the documentation for all SoCs using this code:

Mullins: BKDG #52740 Rev 3.05
Stoneyridge: BKDG #55072 Rev 3.04
Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18
Raven2: PPR #55772 Rev 3.08
Cezanne: PPR #56569 Rev 3.03

The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as
PullUpSel, but this is no longer the case in newer versions. It is
unclear if this got de-featured or if it was never present in the
silicon. To be consistent with the current documentation, drop this
define.

This patch also change the definition of GPIO_PULL_MASK to only cover
the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a
default value of 0 for this bit after reset, so the resulting values in
the register aren't expected change. The other PPRs/BKDGs don't specify
a reset value for this bit, but it's likely safe to assume that all SoCs
that use the new GPIO interface use the same GPIO building block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25 11:07:07 +00:00
Kane Chen 0e9a616c29 soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value
On ADL, we actually use debug consent 2 for soc debug by DBC

Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 10:43:48 +00:00
Rick Lee 8815409ec3 soc/intel/elkhartlake: Update SA DIDs Table
Update SA table as per latest EDS (Doc no: 601458).
Add extra SKUs accordingly.

Signed-off-by: Rick Lee <rick.lee@intel.com>
Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
2021-11-25 10:43:27 +00:00
Ariel_Fang 7fe266d59d mb/google/brya/var/primus: Update thermal table for primus
- Add 4 TEMP_SENSORs
- Configure granularity of power limits

BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25 10:43:08 +00:00
David Wu 3e8ca37b6c mb/google/brya/var/kano: Update thermal table
Update thermal setting from thermal team.

BUG=b:205648035
TEST=build and verified by thermal team.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If5082462b79c88ecf510f7a552381c792604366e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25 10:42:56 +00:00
Raul E Rangel 8928ae380b arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax
The cpu_relax method is defined for x86. This CL adds a no-op method so
that it can be used in common code.

BUG=b:179699789
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-25 10:42:17 +00:00
Arthur Heymans e961033ec4 soc/intel/graphics/Kconfig: Guard options
Change-Id: I3c252e31867e4560fb5aaf12273288f4ff18ae3d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-25 10:41:32 +00:00
David Wu 9ed2490e5b mb/google/brya/var/kano: set power limits for thermal
Set power limits for kano based on CPU SKUs.

BUG=b:205648035
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 10:41:12 +00:00
Subrata Banik 281e2c1987 soc/intel/common/thermal: Refactor thermal block to improve reusability
This patch moves common thermal API between chipsets
with thermal device as PCI device and thermal device behind PMC
into common file (thermal_common.c).

Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC
Kconfig to select as applicable for underlying chipset.

+------------------------------------------------------+--------------+
|               Thermal Kconfig                        |    SoC       |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV        | SKL/KBL, CNL |
|                                                      | till ICL     |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC     | TGL onwards  |
|                                                      | ICL          |
+------------------------------------------------------+--------------+

Either of these two Kconfig internally selects
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs.

BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.

Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 07:18:04 +00:00
Patrick Georgi 673716dedd util/testing: Give meaningful error if intel-sec-tools aren't around
Without manual handling, when 3rdparty/intel-sec-tools isn't around,
`make what-jenkins-does` reports only

    go: go.mod file not found in current directory or any parent directory; see 'go help modules'

which isn't meaningful or actionable. Instead check that the go.mod file
exists and bail out with a better error message before trying to run
`go mod vendor`.

Change-Id: I035747746ca5fd54841bd67352044dde12a28185
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-24 20:16:48 +00:00
Mark Hsieh 05c6d65308 mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble.

BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-24 17:10:01 +00:00
Felix Held 30c1bb60d5 soc/amd/common/block/include/acpi: fix reference to main acpi include
commit e0844636ac (acpi: Move ACPI table
support out of arch/x86 (2/5)) moved the main acpi header file from
arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the
comment in here to point to the current location.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24 17:06:32 +00:00
Felix Held a8820c74b5 soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registers
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585691038690f1d6855ab09f1ca5791a18cfdbfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24 17:05:49 +00:00
Felix Held a31dbb8b8e soc/amd/common/block/include/gpio_defs: use lower case in hex numbers
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24 17:04:40 +00:00
Felix Held 72b92c9207 soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARM
Cezanne already uses a define for this and it's better to define and use
constants instead of magic values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24 17:03:56 +00:00
Jakub Czapiga 7f61d41c1b libpayload/tests: Fix mocks __real_<func> symbol creation
There were escape backslashes around regular expression passed to grep.
Because of that, grep was returning empty results as a consequence of
pattern mismatch, and thus symbols pointing to original functions were
not created correctly.

Change-Id: I751109735b6c56824df9a560ae989bf062a0e9a6
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-24 14:17:01 +00:00
Karthikeyan Ramasubramanian fd6c8d607e drivers/i2c/tpm: Fix blank default statement
CB:59479 introduced a blank default statement. This is treated as an
error or warning on some older toolchains. Add a break statement on
default case.

BUG=None
TEST=Build the Guybrush mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3d034cfebc8b8ae7d7024d41b4b2207cdeb083e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-24 13:45:59 +00:00
Lean Sheng Tan 8e0bfe263c soc/intel/elkhartlake: Disable Intel PSE by default
Disable PSE loading by default. If left enabled (current default),
the EHL coreboot will end up in endless restart loop, due to FSP
unable to locate PSE FW image and trigger global reset.

However disabling this flag (PchPseEnable) will cause the coreboot
to trigger a single reset due to CSE signal (HECI: CSE does not
meet required prerequisites). The reason behind this is that FSP
need to perform static disabling (power gate) to fully shut down
PSE HW, and to do this will need to global reset entire system
including CSE. Then PMC will power gate PSE from the start.

To avoid this behavior, the best way to disable PSE is to disable
via IFWI FIT softstrap (For specific detail can refer to Intel EHL
coreboot MR2 release notes). With this, PMC will power gate PSE
from the first cold boot and system will boot happily without
single reset behavior.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-24 11:19:40 +00:00
Patrick Georgi 7aedf83b30 MAINTAINERS: Remove myself
Change-Id: Ic9dabd0386a32dd1ec0b99e0df3f41f34effc7a3
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-24 11:15:00 +00:00
Jakub Czapiga c69ea3285e libpayload: Add mock assert support for unit testing purposes
Some unit tests might require catching assert failures. This patch adds
an assert() variant depending on __TEST__ define passed to unit tests.

Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-23 23:38:15 +00:00
Jakub Czapiga 162083072e libpayload/tests: remove tests/include/mocks include path
Some files in tests/include/mocks might have the same name as main
libpayload include files. Remove this path from default includes to
force addition of mocks/ prefix in include paths. This will help
avoiding name clashes and will also make mock headers visible.

Change-Id: I4baa07472f0379d56423cf7152b1ecc9a4824539
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-23 23:38:09 +00:00
Evgeny Zinoviev 72628fa813 mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.

On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.

Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.

Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2021-11-23 16:57:14 +00:00
Angel Pons b207f3f370 mb/prodrive/hermes: Number Ethernet devices
The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210
Ethernet NIC, but their numbering isn't consistent with the PCIe root
port function numbers. With only a M.2 SSD plugged in, Linux uses the
following names:

 PHY 0 ---> enp6s0
 PHY 1 ---> enp4s0
 PHY 2 ---> enp3s0
 PHY 3 ---> enp1s0
 PHY 4 ---> enp2s0

These names change after adding or removing PCIe devices in slots
connected to root ports that get enumerated before the NICs' root
ports, because the assignment of secondary bus numbers depends on
the enumeration order. Because of this, the "predictable" network
interface names are not at all predictable, which is awful.

To avoid this, describe the NICs using SMBIOS Type41 entries with the
correct instance numbers. With this patch, Linux uses these names:

 PHY 0 ---> eno0
 PHY 1 ---> eno1
 PHY 2 ---> eno2
 PHY 3 ---> eno3
 PHY 4 ---> eno4

No matter what PCIe devices are present, these names don't change.

Change-Id: I7a527298f84172f9135006083ad7e748dcc27911
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-23 16:56:51 +00:00
Michał Żygowski 8ebea12763 mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs
Enable PCI_EXP_EN, PME_EN and PME_B0_EN GPEs used for PCI devices.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-11-23 16:55:38 +00:00
Michał Żygowski aa133e42ba mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-11-23 16:54:55 +00:00
Tim Crawford 34b70fd163 mb/system76/*: Enable dGPU temp/fan reporting
Select the EC option on boards with dGPUs to report GPU temperature and
fan data.

Tested on system76/oryp6. The GPU fan speed is reported in sensors when
the system is under load.

    system76_acpi-acpi-0
    Adapter: ACPI interface
    CPU fan:     1985 RPM
    GPU fan:     2348 RPM
    CPU temp:     +68.0°C
    GPU temp:      +0.0°C

Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-23 09:22:42 +00:00
Jeremy Soller 924c33b760 ec/system76/ec: acpi: Add dGPU thermal reporting
Add a new config for boards with dGPUs to enable reporting fan duty and
temperature. The dGPU is not yet enabled on any boards, so it always
reports the temp as 0. However, the EC firmware does use the dGPU's fan
and so reports valid information for fan speed.

Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-23 09:22:39 +00:00
Tim Crawford 12a98ffbfb mb/system76/*: Disable IME by CMOS option
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H,
and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER.

The HECI device must be enabled in devicetree for switching modes to
function correctly.

Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-23 09:22:10 +00:00