Commit graph

8913 commits

Author SHA1 Message Date
Felix Held
3136424e48 soc/amd/common/block/acpimmio: add Kconfig option for biosram accessors
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26 19:34:20 +00:00
Angel Pons
ac90f593f8 src/*: Specify type of CBFS_SIZE once
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.

Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:02:57 +00:00
Karthikeyan Ramasubramanian
16f2c5082c soc/intel/jasperlake: Enable support to program VCCIO selection
Jasperlake is one of the few SoCs that support programmable VCCIO
selection and this support is used by Dedede mainboard.

BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.

Change-Id: I54def27a499ccba7fd25cab1048fdca06dbc535f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56536
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:30:59 +00:00
Karthikeyan Ramasubramanian
4c569b52f6 soc/intel/common/block/gpio: Add support to program VCCIO selection
Some of the Intel SoCs with more than 2 PAD configuration registers
support programming VCCIO selection. Add a pad configuration macro to
program VCCIO selection when the GPIO is an output pin.

BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.

Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:30:48 +00:00
Arthur Heymans
a1509d4545 soc/nvidia/tegra124: Increase bootblock size
Verstage even fits in 44K so one can comfortably increase the
bootblock size. This is need for the followup patches that turn
console methods into drivers, which increase the bootblock a little,
but still too much for the the bootblock to fit in the alloted size on
this platform.

Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 05:05:41 +00:00
Ben Kao
6eb5253451 soc/intel/jasperlake: Set xHCI LFPS period sampling off time
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.

The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.

BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26 05:00:51 +00:00
Karthikeyan Ramasubramanian
b3af9f8d2e soc/amd/common/block/pm: Add support for Modern Standby event logging
Log the GPE and PM1 wake events into the event log using the SMI handler
platform callback.

BUG=b:186792595, b:186800045
TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are
logged into the event logs.
5 | 2021-07-15 16:26:43 | S0ix Enter
6 | 2021-07-15 16:26:49 | S0ix Exit
7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22   <- Trackpad
8 | 2021-07-15 16:27:07 | S0ix Enter
9 | 2021-07-15 16:27:13 | S0ix Exit
10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0
25 | 2021-07-15 16:38:13 | S0ix Enter
26 | 2021-07-15 16:38:17 | S0ix Exit
27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint

Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26 04:43:53 +00:00
Karthikeyan Ramasubramanian
589ac69850 soc/amd/common/block/acpi: Extract event logging helpers
Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.

BUG=None
TEST=Build and boot to OS in Guybrush.

Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-26 04:42:54 +00:00
Ravi Kumar Bokka
6668ae3677 sc7280: Increased CBFS_MCACHE size
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-25 05:06:59 +00:00
Felix Held
f070253659 soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bit
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-25 01:14:40 +00:00
Matt Papageorge
5a2feeda39 soc/amd/*/chip.h: Correct PSPP Enum Value
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.

BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.

Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-24 19:49:45 +00:00
Subrata Banik
39b53d9622 soc/intel/common/block: Add space before comment delimiter
Update comment section to add space before comment delimiter to
follow coding style.

Change-Id: I883aeaa9839fa96fd7baf0c771b394409b18ddca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24 11:13:41 +00:00
Felix Held
0b707b9180 soc/amd/common/block/cpu/mca/mca_common: remove additional newline
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-24 00:45:20 +00:00
Felix Held
9a98fc9d1d soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fch
Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 18:03:24 +00:00
Felix Held
f66e781336 soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fch
Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 18:03:15 +00:00
Felix Held
a754aa6d29 soc/amd/picasso/fch: make sb_clk_output_48Mhz static
sb_clk_output_48Mhz is only used in fch.c where it is also implemented,
so no need to have it visible outside of that compilation unit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23 18:03:04 +00:00
Ravi Kumar Bokka
b01b476546 soc/qualcomm: move uart_bitbang UART w/gpio code to common
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22 06:40:06 +00:00
Taniya Das
7a6b2ef25e sc7180: Add target specific GPIO pin definitions
The common gpio driver can be re-used for SC7180,
thus remove the existing gpio driver support and
also clean up the common macro definitions.

Add GPIO pin details specific to SC7180 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.

TEST=Validated on qualcomm sc7180 development board

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-22 06:38:17 +00:00
Felix Held
2eb3ec7563 soc/amd/cezanne/mca: add and use mca_bank_name[]
This enables the MCAX checking and BERT entry generation for Cezanne.

TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706

Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21 22:38:11 +00:00
Kangheui Won
ce0fad5e39 soc/amd/cezanne: enable crypto in psp_verstage
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.

BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-21 16:53:17 +00:00
Raul E Rangel
ce291b4327 commonlib/timestamp,amd/common/block/cpu: Add uCode timestamps
This allows keeping track of how long it takes to load the microcode.

BUG=b:179699789
TEST=Boot guybrush
 112:started reading uCode                             990,448 (10,615)
 113:finished reading uCode                            991,722 (1,274)

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-21 16:43:29 +00:00
Taniya Das
ca74a8f430 soc/qualcomm/sc7280: Replace gpio offset value with macro
Use the gpio offset macro instead of a constant value.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21 16:31:30 +00:00
Ravi Kumar Bokka
a8e9dbae65 sc7180: Renaming the GPIO macro in QSPI and I2C driver
As part of GPIO driver cleanup across qcom chipsets,
GPIO_OUTPUT_ENABLE has been renamed to GPIO_OUTPUT.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21 16:13:54 +00:00
Taniya Das
ec4cc8b2ac soc/qualcomm/common/gpio: Define a macro for the gpio offset
Defining a macro for the gpio offset instead of a constant value.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21 16:08:36 +00:00
Rex-BC Chen
86c50e11ce soc/mediatek/mt8195: modify mt6360 interface
With the new definition of mt6360_regulator_id,
merge the MT6360 LDO and PMIC interfaces into one.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-21 15:46:53 +00:00
Rex-BC Chen
cd67657dea soc/mediatek/mt8195: redefine mt6360_regulator_id
On MT8195 platforms with BC1.2, we have to use EC to control
MT6360 so the mt6360_regulator_id is redefined to match the
numbers defined in EC driver.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21 15:46:09 +00:00
Varshit B Pandya
339f0e7e14 soc/intel/alderlake: Add support for I2C6 and I2C7
As per the EDS revision 1.3 add support for I2C6 and I2C7.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id918d55e48b91993af9de8381995917aef55edc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20 13:35:10 +00:00
Felix Held
aefcab7ff6 soc/amd/picasso/makefile: order source files alphabetically
Change-Id: I6eb0881ab05730b094caef2a9258c4d4d827195b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-20 13:33:37 +00:00
Felix Held
d3a03140dd soc/amd/cezanne/makefile: order source files alphabetically
Change-Id: I4726ba4f19807adf872aaf04764cc19492febd59
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-20 13:33:28 +00:00
Raul E Rangel
21c70b1d0b soc/amd/{cezanne,picasso}: Escape PSP_VERSTAGE_FILE default
If we don't escape the $ then the actual $(obj) path will be written
into the .config file. With this change `$(obj)` is written into the
.config file. The Makefile then does:

    PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))

Since this is a recursive assignment the $(obj) will be expanded at that
point.

This change makes it easier to compare full .config files.

BUG=none
TEST=Build ezkinil

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-07-19 18:22:40 +00:00
Raul E Rangel
73193cf7b7 soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE
This change allows preloading the payload.

BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-19 14:58:53 +00:00
Lean Sheng Tan
750200020a soc/intel/common: Rename kconfig PMC_EPOC
Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain
common naming convention.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-19 06:33:18 +00:00
Raul E Rangel
61f44127f0 soc/amd/cezanne: Start loading APOB asynchronously
This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This
will allow the APOB to start loading while FSP-S executes.

BUG=b:179699789
TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms
to a few uS.

Starting APOB preload
APOB thread running
spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536
 took 0 us to acquire mutex
start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536

<ramstage doing work>

spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0

<more work..>

waiting for thread
 took 0 us
APOB valid copy is already in flash

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:17:30 +00:00
Raul E Rangel
fca58334c8 soc/amd/common/apob: Add support for asynchronously reading APOB_NV
This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.

BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:17:17 +00:00
Raul E Rangel
ce63dc4daa soc/amd/common/apob: Switch to using fmap_locate_area_as_rdev
Using fmap_locate_area is discouraged.

BUG=b:179699789
TEST=Boot guybrush and verify APOB got updated, then reboot and verify
APOB was valid.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f58eace8adb4b7ddaf9047d9b8153405d3941a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56390
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:17:05 +00:00
Raul E Rangel
3af732ada0 soc/amd/common/block/lpc/spi_dma: Yield after completing transaction
There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.

BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:15:27 +00:00
Raul E Rangel
6f3c9018c6 soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers
Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.

BUG=b:179699789
TEST=Boot guybrush with APOB patches.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:15:15 +00:00
Raul E Rangel
d373d5d92f soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.

There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.

BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-18 00:24:09 +00:00
Felix Held
e6dd5dc4ea soc/amd/common/block/graphics: add GPU PCI ID for Barcelo
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.

BUG=b:193888172

Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 21:33:17 +00:00
Felix Held
d5b51beb79 soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.

BUG=b:193888172

Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 21:32:59 +00:00
Meera Ravindranath
81d367feee soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1
Alder Lake supports IGD Opregion version 2.1.

BUG=b:190019970
BRANCH=None

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a6f3df185003a4e38faa920f867ace0b97ab2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 13:48:12 +00:00
Lean Sheng Tan
8d4e67da20 soc/intel/elkhartlake: Expose FIVR config to mainboard
Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.

This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 13:47:25 +00:00
Subrata Banik
8005642936 soc/intel/common/block: Drop unused intelblocks/mp_init.h include
Change-Id: I8621a38214686b359ee0e7cdf7e92154af3cbc81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56381
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 09:51:48 +00:00
Subrata Banik
3b5a47b096 soc/intel/cannonlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I129f169e5dc394a11d8f7b07486cca4894dbec8e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:38 +00:00
Subrata Banik
82f4ca468d soc/intel/elkhartlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: Ieb8063116bee59f6f6bf1f6b0b2349ce22bd67bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-07-17 09:51:25 +00:00
Subrata Banik
94f94f8fb3 soc/intel/jasperlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: Iefc19bc81125f422b8d4fc2f4af60622e7d28c0f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:15 +00:00
Subrata Banik
dbb4e4b241 soc/intel/apollolake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I00ebb9a124eb3b8b893c2b176e14773c05851c18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:06 +00:00
Subrata Banik
8993e67f0a soc/intel/icelake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I97f4d9715f3205678acca8fcdfb1a62714dfaa53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:50:56 +00:00
Subrata Banik
a4a1e6a9b1 soc/intel/skylake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I2123a081baaf6fd254fe81d64eaeee1e3248dd34
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56371
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 09:50:44 +00:00
Subrata Banik
aec071661c soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:32 +00:00