Commit Graph

31141 Commits

Author SHA1 Message Date
Furquan Shaikh fb9f320d81 mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 06:55:05 +00:00
Furquan Shaikh 80212aa104 mb/google/hatch: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard
chip->init(). Additionally, this change moves mainboard_ec_init() to
mainboard dev->init().

TEST=Verified that GPIOs are configured properly and hatch boots to
OS.

Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 06:54:50 +00:00
Cheng-Yi Chiang 91c8d35be3 mb/google/hatch: Set DSM parameters for Helios
Set VPD keys for DSM parameters in overridetree.cb for Helios.
RT1011 driver will load values from VPD and set them to device property.

BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-25 03:12:26 +00:00
Cheng-Yi Chiang 9680b84eb1 mb/google/hatch: Fix speaker mapping for Helios
The correct mapping for speakers to their names should be:

uid 0: Woofer Left
uid 1: Woofer Right
uid 2: Tweeter Left
uid 3: Tweeter Right

Also, fix the name to be 4-character.

BUG=b:140397934, b:143192767
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
And the speaker mapping is correct.

Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 03:12:00 +00:00
Ronak Kanabar 489c10ee54 src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG

Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 02:05:12 +00:00
Peichao Wang 6536084163 mb/google/hatch/var/akemi: Update DPTF thermal sensor for Akemi
Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature

BUG=b:143046086
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
2019-10-24 21:58:55 +00:00
Justin Frodsham ddd02da1de soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from Kconfig
BUG=b:143229128
Change-Id: I03aa12b16979dc07869b0d33daedcde4fe84bc27
Signed-off-by: Justin Frodsham <justin.frodsham@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36281
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 21:11:09 +00:00
Marty E. Plummer 5fc8805a71 Documentation: trivial typo fix strcut/struct
Change-Id: I5e7d8e8a95e5bef23307eb50456a89e0e23c445a
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-24 16:27:47 +00:00
Elyes HAOUAS 0688bce81c src/include/console: Get rid of unused deprecated POST codes
Change-Id: Id577b7c1421e9ffc3f51e90fcc9330c8f3be9a56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-24 16:09:30 +00:00
Tony Huang 81e3b74301 mb/google/octopus: Override VBT selection for Dorp/Vortininja/Vorticon
Add enum for Vorticon sku.

Vortininja/Vorticon will load vbt_vortininja.bin
Dorp will load vbt_dorp.bin

BUG=b:143197918
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
     check i915_drrs_status shows DRRS supported NO
     when SKU-ID sets to Dorp/Vortininja/Vorticon.

Change-Id: I67d7a8ab62a1838b0a0a05f532d8b067ece686d9
Cq-Depend: chrome-internal:2026287
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-10-24 15:52:52 +00:00
Elyes HAOUAS e4b9a1e156 mb/google/{butterfly,link,parrot}: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: I8bcdfa7a4dc33c3e3866d3135249a602379b9615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36265
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 15:52:41 +00:00
Elyes HAOUAS fe3a19d3f3 src/ec/quanta: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 15:52:16 +00:00
Elyes HAOUAS d624e3997a (acpi) superio.asl: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-24 15:52:05 +00:00
Elyes HAOUAS 3128f33c65 ec/google/chromeec/acpi: Drop wrong _ADR object
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 15:51:29 +00:00
Elyes HAOUAS 24cd6c897b soc/intel/apollolake/acpi: Drop wrong _ADR objects for gpio
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: I9f55cc033b5672917520b139444bc614462c4a05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24 15:50:09 +00:00
Yu-Ping Wu ea4bda55d6 soc/mediatek/mt8183: Add udelay after setting voltages
The SOC DRAM team suggested to delay at least 1us after setting new
voltage in PMIC wrapper so the new value can be effective.

BRANCH=kukui
BUG=b:142358843
TEST=emerge-kukui coreboot

Change-Id: I19d236769c3c0c87513ea4a0a3f64b83e3a844c2
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36254
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 15:49:10 +00:00
Johnny Lin 241f0a5593 mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD variables
Add VPD variables for enabling/disabling FRB2 watchdog timer and
setting the timer countdown value. By default it would start the
timer and trigger hard reset when it's expired. The timer is
expected to be stopped later by payload or OS.

Right now the timer is started after FSP-M. Ideally it should be
before FSP-M (to detect memory training error).

Tested on OCP Mono Lake.

Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24 15:47:51 +00:00
Johnny Lin f4abe51b74 drivers/ipmi: Add IPMI BMC FRB2 watchdog timer support
Add a function for initializing and starting FRB2 timer with the
provided countdown and action values, and a stop function for
stopping the timer.

Tested on OCP Monolake.

Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24 15:47:40 +00:00
Werner Zeh 5c18db1ca8 mb/siemens/{mc_apl1, mc_bdx1}: Remove offsets from flashmap files
As fmaptool can now handle the offset computation for every mentioned
region in the fmap file on its own there is no need to provide the
offset in the fmd file anymore. This patch clears this out so that the
files are way more readable now.

Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-10-24 15:47:17 +00:00
Cheng-Yi Chiang d517bff06a mb/google/hatch: Select RT1011 and CHROMEOS_DSM_CALIB for Helios
Use RT1011 driver for Helios. Select CHROMEOS_DSM_CALIB to set device
properties for RT1011 speaker calibration.

BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: I1010be15466c5060aa1d73318393853a2515daac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-24 15:46:25 +00:00
Cheng-Yi Chiang c761f28171 drivers/i2c/rt1011: Add a driver for RT1011
RT1011 is a smart amplifier. It needs to know speaker related parameters
including speaker resistor value and temperature when the calibration is
done in order to run Dynamic Speaker Management (DSM) algorithm on chip.
The purpose of DSM is to protect speaker when the volume is large.

The calibration data of speaker is stored in VPD in factory.
This driver is needed to read data from VPD and write to ACPI _DSD when
config CHROMEOS_DSM_CALIB is turned on.

Kernel rt1011 codec driver will read these device properties to set up
codec accordingly on boot.

The reason to prepare these parameters in coreboot is because kernel
codec driver expects to read per-device parameters directly from device
properties. Another benefit is that other OS can also take these
parameters through ACPI _DSD table and take benefit of DSM on RT1011.

The kernel driver device properties of RT1011 are documented at
linux/Documentation/devicetree/bindings/sound/rt1011.txt
It is currently in ASoC maintainer's tree at
https://kernel.googlesource.com/pub/scm/linux/kernel/git/broonie/sound/+/for-next/
and hopefully should be merged to mainline kernel in the next merge window.

BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24 15:45:53 +00:00
Cheng-Yi Chiang cfde82c1d7 google/chromeos: Add a library to get DSM calibration data
On ChromeOS, there will be VPD values for dynamic speaker management (DSM)
calibration data. They are resistor calibration values and temperature
during calibration.

These VPD fields use "dsm_calib_" prefix.

Known keys are:

"dsm_calib_r0_0"
"dsm_calib_r0_1"
"dsm_calib_r0_2"
"dsm_calib_r0_3"
"dsm_calib_temp_0"

For now these values are unsigned decimal numbers greater than 0.
This library will be used for RT1011 device driver in the patch series.

Note that in the future we may encode more values into this VPD field if
needed. We retain the flexibility for coreboot device driver or codec
driver to decode/parse the VPD values based on the needed use case
per-board.

BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: Ib9579a5cc055f8f438cb30a8acaf250a343db19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24 15:45:37 +00:00
Elyes HAOUAS fcdb03358d acpi: Drop wrong _ADR objects for PCI host bridges
Found-by: ACPICA 20191018
Change-Id: I81286d89da933b503f605737f28772bfb08483a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36253
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 09:28:28 +00:00
Yu-Ping Wu 85ca1fe4e6 soc/mediatek/mt8183: Improve DRAM calibration logs
- Add macro dramc_err.
- Some log levels are changed.
- Some messages are improved for readability.

BRANCH=kukui
BUG=none
TEST=emerge-kukui coreboot

Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 07:51:51 +00:00
Yu-Ping Wu c5568a145f soc/mediatek/mt8183: Correct continuation line indent
BRANCH=kukui
BUG=none
TEST=emerge-kukui coreboot

Change-Id: I9d01d24d3494f2eb28cfb411e13adf3b6717d191
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36285
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 07:51:36 +00:00
Uwe Poeche ed309e58b0 soc/intel/fsp_baytrail: use designware I2C driver
Refactor I2C driver for fsp_baytrail to match the coreboot supported I2C
bus device structure. The internal I2C controllers are now handled by
the generic PCI driver approach and generic I2C access is enabled.
As orientation for the I2C code the actual solution from
soc/intel/apollolake I2C was taken. All the I2C specific parts were
removed from lpss.c and have been implemented in the I2C driver.
Future merge to soc/intel/common/block/i2c/i2c.c would be possible.

With this patch I2C chip devices can now be used in devicetree.

TEST=Booted siemens/tcu3 and verified that access to PTN3460 worked.

Change-Id: I3b87bd7c27e4c1afcce7cd4225cca02599f43c60
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-24 07:50:02 +00:00
Hung-Te Lin 285975dbba soc/mediatek/mt8183: Force retraining memory if requested
To allow retraining memory without hotkey (for example in manufacturing
process), we want to enforce re-training when the recovery reason is set
to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running
 "crossystem recovery_request=0xc4").

The special reason was created for X86 MRC cache, for ensuring RO
calibration data is filled (the underlying implementation was in vboot,
not coreboot); and on MT8183 we have only RW calibration, but it seems
totally fine to extend that for RW.

BRANCH=kukui
BUG=None
TEST=boots; crossystem recovery_reason=0xc4; reboot

Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-24 07:45:55 +00:00
Himanshu Sahdev 7f1da07849 arch/acpi.h: Use of typedef for acpi_vfct
Use of typedef and modify the usage accordingly.

Change-Id: I875ef2fa31e65750233fa8da2b76d8db5db44f2d
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-24 07:44:53 +00:00
Himanshu Sahdev afd0505033 arch/acpi.h: Use of typedef for acpi_vfct_image_hdr
Use of typedef and modify the usage accordingly.

Change-Id: I65581702a60dbd286cb3910c6eeef5f9e1853cf1
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-24 07:44:34 +00:00
Michael Niewöhner bc36e298f9 soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add
ELOG wake sources for ports 13-24, if they exist.

Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24 07:43:11 +00:00
Michael Niewöhner 1b79b86def mb/supermicro/x11-lga1151-series: enable SLP_S0 as vendor does
This enables SLP_S0 for x11 boards.

Change-Id: I7240ed631bf72b1d3c9ea887da43772781c80b45
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24 07:42:08 +00:00
Peter Lemenkov 7398c95d9c mb/lenovo/t410/board_info: Add release year field
Change-Id: I24b92977ab1259159d2d21dfb355ea5d53bfb141
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36204
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 07:41:05 +00:00
Patrick Rudolph 980d704b4d cpu/intel/common: Enable GetSec leaves for Intel TXT
Similar to VMX and SMX also enable all GetSec leaves for Intel TXT.

Change-Id: I89620c2a98cfceaa785b1a798fafbf35cc99a0b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-24 07:40:01 +00:00
Patrick Rudolph 59ba0a257a soc/intel/fsp_broadwell_de: Add function to set DPR
Add code for FSP Broadwell DE to set the DPR.
Used by the Intel TXT code.

Tested on Intel Broadwell DE using Intel TXT.

Change-Id: Ib5e1ba8731e5cea1be9319a1fb9658dba841dc7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-24 07:39:22 +00:00
Michael Niewöhner 7bdedcdc33 soc/intel/skylake: lock AES-NI MSR
Lock AES-NI register to prevent unintended disabling, as suggested by the
MSR datasheet.

Successfully tested by reading the MSR on X11SSM-F

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35188
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23 20:39:44 +00:00
Arthur Heymans 88e9c5af57 drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set_option
Avoid searching for cmos_layout.bin each time get/set_option is called
on platforms with NO_CAR_GLOBAL_MIGRATION.

Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-23 14:23:29 +00:00
Arthur Heymans 62a6741bba Documentation: Add a technote section
Change-Id: I8676f89399a0def3409f19dc92e4f65924d0ba22
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-23 14:22:58 +00:00
Arthur Heymans 750ce06cd5 technotes/coreboot-image-generation: Fix markdown
The manifest example has to be marked as code. The Manifest parsing
section header should be L2 and finally # is a special character in
markdown.

Change-Id: I38cb1a508ec9ccb39cb39048de3742a5cb595f7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-23 14:22:55 +00:00
Michael Niewöhner 7f2aaacd9e mb/supermicro/x11-lga1151-series: add x11ssm-f board
This adds another x11 series board, the X11SSM-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and
Ethernet interfaces.

Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
2019-10-23 14:21:40 +00:00
Vladimir Serbinenko d2aa4730e3 mb/{lenovo/x201,packardbell/ms2290}/acpi: Merge common platform ASL code
This code in reality just describes the southbridge features, don't put a copy
in every mainboard.

This commit follows up on commit e288758b with Change-Id
I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 ("bd82x6x: Merge common
platform ASL code").

Change-Id: Ic5260461165b794a13efd2c6d968c953f60dd253
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36229
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23 13:36:15 +00:00
Yu-Ping Wu 42ec48032a soc/mediatek/mt8183: Fix incorrect usage of sizeof
BRANCH=kukui
BUG=none
TEST=emerge-kukui coreboot

Change-Id: Ic2f6bfaf42aed642e1d7d6aba5db373944eb8ef6
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-23 13:35:59 +00:00
Jitao Shi b6ca93839d soc/mediatek/mt8183: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo error.

BUG=b:139150763
BRANCH=kukui
TEST=Boots correctly on kukui

Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-23 13:35:41 +00:00
Jitao Shi 19e961e83c soc/mediatek/mt8183: fine tune the phy timing
To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.

BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui

Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-23 13:35:26 +00:00
Peter Lemenkov 68ff7298ec mb/lenovo/t410/dock: Remove unused includes
Change-Id: Ia1df27b6d946d8ef5252cc35bb4fcaaabedbe2c7
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-23 13:35:07 +00:00
Peter Lemenkov 0a793d85f1 mb/lenovo/t410/early_init: Remove unused include delay.h
Change-Id: I22b78a976c6ea43caa326e990a3c3333fef99d61
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-22 20:10:58 +00:00
Kane Chen 0bc35af933 mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch
On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode.
VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted.

This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can
program related setttings to save power.

BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles

Change-Id: Ia02ff8823883489b36349457213409496f082f36
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-22 20:10:28 +00:00
Kane Chen 58e96705cb soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE
The previous code actually set SlpS0WithGbeSupport even when GBE is
disabled in device tree and could cause power consumption in s0ix.

This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport,
PchPmSlpS0Vm075VSupport by device tree.

SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled.

BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles

Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-22 20:10:08 +00:00
Jacob Garber 61a2d25a01 soc/nvidia/tegra124: Fix null pointer and logic bug
Commit 680027edf6 fixed a null dereference and logic bug in the tegra210
spi code:

    soc/nvidia/tegra210: Fix potential NULL pointer dereference

    Recent Coverity scan indicated potential NULL deference; if either
    spi->dma_in or spi->dma_out are NULL, the fifo_error() check could
    dereference a NULL pointer.

    Also fixed what appears to be a logic bug for the spi->dma_out case,
    where it was using the todo (count) from spi->dma_in.

Coverity is warning about the same problem for tegra124, so apply the
same fix there. Also, add braces around a while statement.

Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 124183, 124185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22 20:08:20 +00:00
Arthur Heymans 39bde7cacf sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platforms
This follows the ICH7 datasheets.

Change-Id: Ic8f6db8556662b03efead8c1b9e3074ffe24cd8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36201
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22 20:07:11 +00:00
Peter Lemenkov ebcb0c5b88 mb/lenovo/t410/gpio: Use static for const structures
Autoport generates these structures as static so let's make it consistent.

This commit follows up on commit 6752b615 with Change-Id
I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for
const structures").

Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22 20:06:53 +00:00