Commit Graph

10598 Commits

Author SHA1 Message Date
Edward O'Callaghan 49380b87d1 superio/smsc/fdc37n972: Trivial cleanup reorder headers
Alphabetise headers and a few trivial cleanups.

Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6042
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-21 00:02:14 +02:00
Dave Frodin 29179f0735 superio/nuvoton: Add chip support for setting IRQs to edge/level
Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-20 23:29:27 +02:00
Dave Frodin da2daef4b4 superio/nuvoton: Adds a function to route pins 41-48 to UARTD
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.

Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20 23:28:59 +02:00
Edward O'Callaghan 7bf4f484c0 southbridge/intel/lynxpoint/me_9.x.c: Use IS_ENABLED macro
Silence unused function warnings, spotted by Clang.

Change-Id: I5127893e9605ca490ff450faa92af5e9eafe8940
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6054
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20 22:43:02 +02:00
Edward O'Callaghan 22e9e66cac superio/ite/it8772f: Remove prototypes for func with no body
Change-Id: Iaf5db7153b08ac81b233f967c7a604ed08af91ca
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6040
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20 22:37:11 +02:00
Edward O'Callaghan 114f0ee9d4 src/mainboard/google/*/mainboard_smi.c: Remove #include .c's
No need for these.

Change-Id: I1df6e2ef06bd5546a66ee05a15fa2f7c3daf8853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6039
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20 22:36:19 +02:00
Paul Menzel 4c960d4ebe google/link, lenovo/x60: i915io.c: Use define `ARRAY_SIZE`
Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5936
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-20 22:29:50 +02:00
Edward O'Callaghan d309eb145d mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changes
Port to recent reference board (AMD Persimmon) changes in commits:

c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing

Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5882
Tested-by: build bot (Jenkins)
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-06-20 19:54:39 +02:00
Kyösti Mälkki 4d9b77287e ACPI: Add acpi_is_wakeup_s3()
Test explicitly for S3 resume.
Also switch to use IS_ENABLED().

Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6070
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20 19:52:40 +02:00
Kyösti Mälkki 6722f8da40 sandy/ivy boards: Use acpi_s3_resume_allowed()
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6063
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:51:16 +02:00
Kyösti Mälkki bb805e156a nehalem boards: Use acpi_s3_resume_allowed()
Also update packardbell/ms2290 to match lenovo/x201.

Change-Id: I6bda740cadd81ebe47e57742c507bff322a9fb0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6062
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:51:04 +02:00
Kyösti Mälkki 12d681b23f intel/i945 gm45: Use acpi_s3_resume_allowed()
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6061
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:50:50 +02:00
Kyösti Mälkki 2ca2afe760 ACPI S3 support: Add acpi_s3_resume_allowed()
Add this to reduce the amount of preprocessor conditionals used in the source,
compiler currently resolves this to a constant.

Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change
the implementation to enable/disable S3 support runtime.

Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6060
Tested-by: build bot (Jenkins)
2014-06-20 19:50:04 +02:00
Kyösti Mälkki b3594ab489 util/cbmem: Workaround for IS_ENABLED()
Our include files reference CONFIG_xxx declarations, which we should
ignore for utility build.

We cannot include kconfig.h to get IS_ENABLED() as that file
would require build/config.h and we do not want to enforce a build
of the firmware to be able to build the utility.

Since we do not include build/config.h each occurence of CONFIG_xxx
in the included header files is undefined and will be treated as
disabled.

Change-Id: I74f1627fc3f294410db8ce486ab553dac9e967f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6066
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20 19:49:11 +02:00
Edward O'Callaghan 8fac0b3e90 src/lib/clog2.c: Fix style and clarity, remove some cruft
Change-Id: I6b37cf945db12d2cf8096c9f49fff9e0bec139d6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6058
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-20 08:06:51 +02:00
Edward O'Callaghan 669cb2f0c4 drivers/intel/gma: Equality comparison with extraneous parentheses
Spotted by Clang.

Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6053
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-20 07:36:31 +02:00
Kyösti Mälkki 3722f3c3f5 supermicro/h8scm: Fix Kconfig
Change-Id: I0ecc3c5a26251f248234244bf305d3e13e41b9e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6069
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-19 23:05:10 +02:00
Kyösti Mälkki 17290e4b6c intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INIT
This is implied from DYNAMIC_CBMEM from soc/.

Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6029
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-18 23:15:20 +02:00
Martin Roth de38eeaaa6 fsp_baytrail: Add the default FSP location
The default FSP location needs to be in the chipset, not the mainboard.
This was removed from the Bayley Bay mainboard in patch 41ea7230f7
reviewed at http://review.coreboot.org/#/c/5982/

Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5985
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2014-06-18 22:24:54 +02:00
Martin Roth c0602d4cab fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode
- Add the Bay Trail B0/B1 microcode.  These versions of the SOC were
released as a "Super SKU" which had features of all the different
SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the
number 2 in the third character from the left in the microcode name.

- Update the size of the microcode blob.  We should be pushing a patch
to eliminate the need for this shortly.

Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-18 22:11:05 +02:00
Edward O'Callaghan c94d73e0e6 mainboard: Clear up remaining SIO_PORT from Kconfig
Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.

Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18 21:17:27 +02:00
Edward O'Callaghan 401b8accf8 mainboard/amd,lippert: Drop SIO_PORT from Kconfig
CONFIG_SIO_PORT is not used anywhere and should not be here any way.

Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6044
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18 21:17:21 +02:00
Edward O'Callaghan dfc0c13b1a mainboard/jetway/nf81-t56n-lf: Drop SIO_PORT from Kconfig
CONFIG_SIO_PORT is not used anywhere and should not be here any way.

Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6043
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18 21:17:14 +02:00
Kyösti Mälkki a0b4a8d819 ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.

Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-18 20:37:34 +02:00
Kyösti Mälkki c862e44162 northbridge/intel: Drop use of set_top_of_ram()
We implement get_top_of_ram() on these chipset to resolve CBMEM
location early in romstage. Call to set_top_ram() is not required.

Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-18 20:36:56 +02:00
Kyösti Mälkki 191d221920 intel/nehalem: Add get_top_top_ram() in ramstage
Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM
set_top_of_ram() will no longer be available.

Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-18 20:36:08 +02:00
Kyösti Mälkki aac45febc7 emulation/x86 : Drop HAVE_ACPI_RESUME
S3 resume detection not implemented in romstage.c.

Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6028
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-18 20:30:45 +02:00
Kyösti Mälkki a1e924ca6b mainboard/supermicro/h8dme: Drop unused code
Clang complains about a unused debug function, so remove dead code.
We have copy of dump_smbus_registers() in amdk8/debug.c.

Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5942
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-18 20:29:24 +02:00
Kyösti Mälkki f565ab0e25 lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT
Use the value from hardware for uma_memory_base.

Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-18 20:28:58 +02:00
Vladimir Serbinenko cc483aee96 intel/model_2065x: Add 20652 microcode.
Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5117
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-17 21:31:01 +02:00
Mike Loptien cbc783f3e1 Persimmon: Change MPTable to use mainboard IRQ routing
With the addition of the mainboard PCI IRQ routing tables
for AMD Persimmon, the MPTables can be set to use this
information to accurately reflect the real hardware settings
of the system.  Additionally, the IOAPIC gets defined before
the MPTable gets generated so the settings can be read
directly from the IOAPIC registers instead of 'guessing' at
them as was done before.

Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5878
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-16 18:38:47 +02:00
Mike Loptien d0167d3ae2 MP Spec: Correct the Virtual Wire assignment
Virtual Wire mode is set by writing 0 to the the MPTable
Feature2 bit field 'IMCR'.  The virtualwire variable was
initially defined as writing a 1 to this bit field which
would actually set PIC mode instead of Virtual Wire mode.
However, nearly every mainboard called the MPTables with
virtualwire = 0, which actually had the effect of setting
Virtual Wire mode. I am correcting the definition but
leaving the call to write the MPTables with virtualwire = 0,
which is how most mainboards are already setting the tables
up.

See the MP Spec table 4-1 for more details:
	Bit 7: IMCRP. When the IMCR presence bit is
	set, the IMCR is present and PIC Mode is
	implemented; otherwise, Virtual Wire Mode is
	implemented.

http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf

Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-16 18:14:35 +02:00
Mike Loptien 9159734065 MP Spec: Add copyright header
Adding the copyright header to the MP Spec files because
they were not included before.

Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5981
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-16 18:14:18 +02:00
Edward O'Callaghan f7d8f09d76 amd/agesa,cimx: Rename ACPI OS detection methods
Try to 'standardize' the otherwise peculiar method naming to be somewhat
more in-line with other ACPI implementations. This makes it easier to
compare with vendor DSDT dumps for example.

Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5888
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14 20:47:57 +02:00
Edward O'Callaghan 7a22b0976c amd/agesa/f15tn: Invalid inline asm in gcc-intrin.h
Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm

Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5941
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14 20:46:26 +02:00
Edward O'Callaghan 3628f93cf5 mainboard/ibase/mb899: Break out superio hwm conf from mainboard
Break out the PNP Super I/O HWM configuration from mainboard.c

Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5797
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14 20:42:11 +02:00
Edward O'Callaghan e93fe23440 amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.c
Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5802
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14 20:38:49 +02:00
Edward O'Callaghan cd30951e32 mainboard/amd: De-ASCIIartify reference boards
For anyone who knows the difference between a header and a variable in C
these depictions are rather useless. Thus, these lines wast essential
screen real estate while working on coreboot.

Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5979
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-14 20:32:27 +02:00
Martin Roth 0baaa2d5a7 fsp_baytrail: remove version from default vbios path
Intel requested that we remove the version number from the default
vbios path.

Change-Id: I2590fed0db157e3e430212336fc55eb099d28a72
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-13 23:32:49 +02:00
Martin Roth d866e5872d fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT
While pushing the fsp_baytrail code, it was requested that we change
CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT.

These were missed in the change.

Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5972
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-13 18:34:04 +02:00
Paul Menzel 4dfc50b877 mainboard.c: Fix typo in appro*p*riate in comment
Use the following command to fix all occurences.

	$ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g'

Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5987
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-13 09:39:28 +02:00
Dave Frodin 9b800ae954 southbridge/amd: Change #if defined to #if IS_ENABLED
The IMC functions were being called and timing out when the
CONFIG_SB800_IMC_FWM/CONFIG_HUDSON_IMC_FWM were defined as 0.
Changing to a IS_ENABLED will keep the IMC handshake from
occuring if the IMC firmware isn't running.

Tested on a Persimmon platform which makes three calls to
spi_claim_bus() with each call timing out after 500ms.

Change-Id: I5d4bbcecf003b93704553b495a16bcd15f66763b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5974
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-12 20:13:21 +02:00
Martin Roth 41ea7230f7 bayleybay_fsp Kconfig: Remove unnecessary overrides
Use the default mmconf base address and fsp locations.

Change-Id: Ia9116b0f0fc799592df2a10b10e086cfc88b394c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-12 20:10:23 +02:00
Kyösti Mälkki 33eaf3a715 superio/smscsuperio: Fix chip detection
There was dereference of NULL dev->ops in pnp_enter/exit_conf_mode()
as those calls were made before pnp_enable_devices() was run.
Since hardware did not enter configuration mode, detection failed with
ID and REV read as 0xff.

Change-Id: If13086707cd86e392890ccf4f717e13a87f3317f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5949
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-06-12 15:10:37 +02:00
Vladimir Serbinenko afc8d98769 intel/bd82x6x: Skip unknown MBP.
Allow skipping unknown MBP rather than bailing out.

Change-Id: I9a54858c37d73e320de77aea5a05ab5dcf67cd69
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5976
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-12 14:57:15 +02:00
Paul Menzel 209238755a device/device_util.c: Fix wording in comment of `new_resource()`
Change-Id: Ieb0d5de37870a359f3a7ea1543640e26f86c1684
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5952
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 20:37:50 +02:00
Dave Frodin ac1b875b55 amd/southbridge/lpc: SPI BAR has fixed size/location
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.

Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 20:06:21 +02:00
Vladimir Serbinenko 61f902d4a7 ibexpeak: Set number of USB ports.
Change-Id: Ife3febcc88967386dfae624cd237562a34a68471
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5956
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 19:43:46 +02:00
Vladimir Serbinenko 49c3045c2d ibexpeak: Remove some dead code.
Change-Id: I68ae49d20a2524f03c4503f2b3be93f07b9cb6e3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5955
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 19:43:36 +02:00
Mike Loptien c93a75a5ab AMD/CIMx: Add functions for AMD PCI IRQ routing
The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01.  This table is responsible for physically
routing IRQs to the PIC and IOAPIC.  The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.

The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately.  This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts.  It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table.  It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE.  Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.

For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2.  This corresponds to PIN B.  On the
Persimmon mainboard, I want the USB device to use IRQ 11.  I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11.  This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read.  It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.

Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.

Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.

Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-11 17:07:50 +02:00