Commit Graph

6342 Commits

Author SHA1 Message Date
Stefan Reinauer 334532eeff Add Sandybridge/Cougar Point support to SMM relocation handler
Previously this part of smmrelocate.S had to be omitted because
the CONFIG_ options for those components did not exist yet. Add
them back.

Change-Id: I6ac94ca804e03062724401a08d1d174adac5e830
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/874
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2012-04-06 02:15:34 +02:00
Stefan Reinauer c00dfbc1c8 Cache 8MB flash instead of 4MB
Also fix the MTRR check to use the total_mtrrs
variable instead of a hardcoded 8.

Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/873
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-06 02:13:27 +02:00
Stefan Reinauer 6293d30768 Factor out function to find driver for a CPU
This function can be used outside of the normal CPU setup

Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/868
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-06 02:13:12 +02:00
Stefan Reinauer 61f4a744c0 Add constants for fast path resume copying
cache as ram does not usually cache the ram before it is up. Hence,
if romstage.c backs up resume memory, the involved memcpy is always
uncached. This makes resume very slow.
On Sandybridge we copy the memory later, after enabling caching, and
that allows us to resume in as little as 250ms.

Change-Id: I31a71ad4468679d39880cf9a8c4e497bb7addf8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/872
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-04-06 00:33:16 +02:00
Stefan Reinauer 5b6404e419 Fix timer frequency detection on Sandybridge
Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/870
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-04-05 23:35:13 +02:00
Bernhard Urban cab72d9b7b amdfam10: add phenom II as known cpu
Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7
Signed-off-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-on: http://review.coreboot.org/864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 23:12:24 +02:00
Stefan Reinauer deda997833 Invalidate cache before first jump
Some CPUs (Sandybridge) seem to require this, and it does not hurt
on other CPUs.

Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/869
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-04-05 23:03:09 +02:00
Stefan Reinauer c6b2166d89 smbios: Don't fill out firmware version on ChromeOS
In ChromeOS we potentially have different payloads with
different versions. Since the user land tools get information
on which one of them is loaded, leave the string in smbios
empty so we can fill it out in the payload.
Also fill out system version number and serial number with
some constant values.

Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/867
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-04-05 22:47:22 +02:00
Stefan Reinauer 31324c64e1 Fill out ChromeOS specific coreboot table extensions
ChromeOS uses two extensions to the coreboot table:
- ChromeOS specific GPIO description for onboard switches
- position of verified boot area in nvram

Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/866
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 22:47:13 +02:00
Stefan Reinauer 8c5b58e7c3 Update documentation in smmrelocate.S to mention TSEG
Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/861
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-05 22:01:35 +02:00
Stefan Reinauer 5c55463f50 Add support for Intel Sandybridge CPU
Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/855
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 21:10:25 +02:00
Stefan Reinauer 00636b0dae Add support for Intel Sandybridge CPU (northbridge part)
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/854
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 20:59:31 +02:00
Patrick Georgi 4dd3853437 Ignore .exe files in whitespace test
On windows, we sometimes require getopt executables, which end up
in the source tree. These shouldn't break the whitespace test.

Change-Id: Iaf86e38b94605bebb69a317e00f932eefcf468b9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/863
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 20:50:52 +02:00
Patrick Georgi 92cfe183a7 Add getopt implementation to abuild
Similar to buildgcc, abuild requires getopt(1). Provide an
implementation for platforms without it (Win32)

Change-Id: I2ae4d84e06dd34135c97b18819da2b49a89706ce
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/862
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 20:50:46 +02:00
Stefan Reinauer fb89dd0a93 Use fast memset in SMM mode, too
... and always include IP checksumming in romstage.
It's generally useful and our upcoming port needs it.

Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/827
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 19:45:10 +02:00
Stefan Reinauer 8e073829ec Add support for Intel Panther Point PCH
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 19:10:51 +02:00
Stefan Reinauer cb91e1525e Add support for mainboard specific suspend/resume handler
Some mainboards (most likely laptops) will need mainboard specific functions
called upon a resume from suspend.

Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/852
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 19:10:28 +02:00
Stefan Reinauer ec207630a5 Move TPM code to romstage
We want to do TPM initialization as early as possible to keep
the impact on boot time low. Therefore move it to romstage.

Change-Id: I5f2e021e0b11bd70a78ad1f05ec09802d015dd9e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/856
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 19:09:53 +02:00
Stefan Reinauer 15511835b9 Drop verified boot code from acpi.c
We changed our verified boot initialization to run from romstage,
as that allows faster boot times and does not add as much ChromeOS
specific code to generic files.

Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/851
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 18:00:22 +02:00
Stefan Reinauer f13772af9f Drop duplicate inclusion of src/vendorcode
Change-Id: I95908bdca51c5ee959ae9f2307d4b6e0e002d04a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/857
Reviewed-by: Martin Roth <martin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-04-04 16:21:51 +02:00
Stefan Reinauer 3aa067f595 Add support to run SMM handler in TSEG instead of ASEG
Traditionally coreboot's SMM handler runs in ASEG (0xa0000),
"behind" the graphics memory. This approach has two issues:
- It limits the possible size of the SMM handler (and the
  number of CPUs supported in a system)
- It's not considered a supported path anymore in newer CPUs.

Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/842
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-04-04 04:49:09 +02:00
Mathias Krause 6efbebdb58 libpayload: avoid excessive casts in printf.c
struct printf_spec is a purely internal structure. Avoid excessive casts
when using the write function pointer just to make the compiler happy by
using the right types in the first place.

Change-Id: Ia4f3c79a5283cb76c8aa5f9d1eee758676303382
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/850
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-04 00:41:57 +02:00
Mathias Krause 67997d330d libpayload: minor cleanups
Apply some const correctness to const/non-const strings in libc and
libpci (what an ugly cast that was).

Remove duplicated NULL test in printf_putstr(), already done in
print_string() - reduces size of libpayload by a few bytes.

Change-Id: I13f479df13e39d79cab291e9d99d153e1ef43eae
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-04 00:40:31 +02:00
Stefan Reinauer f17789c4ff Don't unconditionally show ChromeOS options
Google ChromeOS specific options were shown in the main menu
unconditionally, even on non-ChromeOS devices. Instead, hide
these options unless CONFIG_CHROMEOS is set, and also put them
in a separate menu.

Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/848
Reviewed-by: Martin Roth <martin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-04-04 00:36:27 +02:00
Stefan Reinauer ea37a21acf Add support for Intel Turbo Boost feature
From wikipedia:
Intel Turbo Boost is a technology implemented by Intel in certain
versions of their Nehalem- and Sandy Bridge-based CPUs, including Core
i5 and Core i7 that enables the processor to run above its base
operating frequency via dynamic control of the CPU's "clock rate".
It is activated when the operating system requests the highest
performance state of the processor.

Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/844
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-03 20:29:33 +02:00
Stefan Reinauer 3d7c6770c4 smbios: add support for onboard devices extended information
Add support for type 41 smbios tables (to be used by board
specific smbios handlers)

Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/843
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-03 19:35:26 +02:00
Patrick Georgi 4a2daf6a99 nvramtool: 64bit safe CBFS handling
Change-Id: I4f23ee04cd6479e55e9467af1b0196936412deb1
Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/846
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-03 18:33:47 +02:00
Patrick Georgi 3bbd2bfa1c Add preprocessing capabilities to the cbfs-files mechanism
It's now possible to generate files that are about to be added to
CBFS by specifying "sourcefile:method" as real file name.

This makes the build system use the cbfs-files-preprocessor-$(method)
function to create a file from sourcefile. That generated file is
then added to CBFS.

The first method to be defined is "nvramtool". It expects a plain text
specification of the CMOS configuration and emits the binary format
suitable for cmos.default.

Change-Id: I33a142718fc7238eaf5317b0ed62b4726d9b48f2
Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-03 18:33:23 +02:00
Patrick Georgi 499fc926f8 Add nvramtool to coreboot build system
This way we can depend on it during build.

Change-Id: I7e773c6a029e376e3d70d0a8c9e96ffe0c2cf82e
Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-03 18:32:23 +02:00
Kyösti Mälkki abdf15f40b Apply cache-as-ram conditionally on socket mPGA604
The socket mPGA604 is for P4 Xeon which to my knowledge is always
HT-enabled. I assume the existing usage of car/cache_as_ram.inc
on socket_mPGA604, namely the Tyan S2735, as broken.

Existing car/cache_as_ram.inc has invalid SIPI vector and it does
not initialise AP CPU's to activate L2 cache.

Other mPGA604 boards are not affected, as they have not been
converted to CAR.

Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/607
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 21:13:26 +02:00
zbao afd141d504 S3 code whitespaces changes.
some blank changing is integrated into the previous patches, which hold
the unsplitted diff hunk.

Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02 21:11:54 +02:00
zbao 01bd79ff69 Add sb800 spi support.
It is for S3, storing the recovring data in the nonvolatile storage,
i.e., flash.

Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/620
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02 20:35:03 +02:00
Mathias Krause 971804ed68 x86, oprom: ensure DF is always cleared
The Option ROM might mess with the EFLAGS register and break assumptions
the C part of coreboot implicitly has, e.g. the state of the direction
flag.

Prevent Option ROMs from confusing coreboot by restoring the old EFLAGS
value after the Option ROMs has finished and always clear the direction
flag before calling the C part of the interrupt handler.

Change-Id: I84663be6681b17f95f48d93f0b730e443336b4a8
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/837
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-02 19:50:22 +02:00
Stefan Reinauer 74a0efe09a [ChromeOS] Don't initialize VGA Option ROM in normal mode
ChromeOS features two different modes: normal mode and developer mode
(aka jailbreak mode). In developer mode, we need to display a warning
screen for security reasons.

However, in normal mode we want to boot blazingly fast. Therefore we
don't run (VGA) option ROMs, unless we have to print something on the
screen before the kernel is loaded.

Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/829
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:42:54 +02:00
Stefan Reinauer 020b22a5c4 Add EC component for SMSC MEC1308/1310
Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/828
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:42:40 +02:00
Stefan Reinauer b0dd1d91f4 Add support for ITE IT8772F SuperI/O chip
Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/822
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:40:10 +02:00
Stefan Reinauer dc8448fd8b Add a helper function to determine the number of enabled CPUs
Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/821
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:39:58 +02:00
Stefan Reinauer d40393e390 Align: Make sure 1 is treated as unsigned long instead of int
... and drop duplicate definition in via/epia-n code.

Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/820
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:39:48 +02:00
Stefan Reinauer 9aea04aa89 Add Google ChromeOS vendor support
Google's ChromeOS can be booted super fast and safely
using coreboot. This adds the ChromeOS specific code that
is required by all ChromeBooks to do this.

Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/817
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:39:31 +02:00
Vadim Bendebury c302d20ed3 Force coreboot mconf to create temp files in the output directory
This change partially addresses the problem with attempting to
generate coreboot image out of tree. The configuration step fails when
in cheroot, if the destination directory is placed in /tmp.

The problem is that the mconf package tries renaming the temporary
file created in the local directory into the destination config file.
If the destination root and the local directory are located on
different file systems, the rename operation fails.

The proper fix (still upcoming) would be to identify all places where
mconf creates temp files, and make sure that all temp files get
created in the destination tree.

This change modifies just one location, which prevents building out of
tree in the most common case.

Test:
  run the following in the coreboot directory in chroot:
    (coreboot) cp config.lumpy .config
    (coreboot) /bin/rm -rf /tmp/cb
    (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb oldconfig
    (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb

  Observe the build succeed (it was failing during the config phase
  before this change)

Change-Id: If4506e984b8afc192a1689c7b0aa956dd35f66c6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:39:22 +02:00
Gabe Black e1bb49e2ec Add a "remove" command to cbfstool
This command removes the first file it finds with the given name by changing
its type to CBFS_COMPONENT_NULL and setting the first character of its name to
a null terminator. If the "files" immediately before or after the target file
are already marked as empty, they're all merged together into one large file.

Change-Id: Idc6b2a4c355c3f039c2ccae81866e3ed6035539b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/814
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:39:08 +02:00
Mathias Krause dd30acdd59 Fix issues with x86 memcpy
The x86 memcpy() implementation did not mention its implicit output
registers ESI, EDI and ECX which might make this code miscompile when
the compiler uses the value of EDI for the return value *after* the 'rep
movsb' has completed. That would break the API of memcpy as this would
return 'dst+len' instead of 'dst'.

Fix this possible bug by removing the wrong comment and listing all
output registers as such (using dummy stack variables that get optimized
away).

Also the leading 'cld' is superflous as the ABI mandates the direction
flag to be cleared all the time when we're in C (see
<http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites
that might require it to be cleared explicitly (SMM might come to mind,
but it clears the DF itself before passing control to the C part of the
SMI handler).

Last but not least fix the prototype to match the one from <string.h>.

Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/836
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-31 20:26:20 +02:00
Patrick Georgi 819c7d4a35 Whitespace fixes
Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/834
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-31 18:06:09 +02:00
Marc Jones 087b24db2d Update xcompile to search for x86_64 toolchain.
This adds detection of x86_64 gcc toolchain (which buildgcc can build
if provided the option).

Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/673
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
2012-03-31 12:49:45 +02:00
Gabe Black b9fa1ed5e8 Make libpayload parse the coreboot tables before setting up the consoles
At least one of the console drivers, coreboot fb, uses information in the
sysinfo structure to set itself up. If that structure hasn't been populated,
the driver decides that there is no framebuffer and disables itself. Reversing
the order these are set up fixes that problem.

Change-Id: Idd8b5518980dfdd82fd4359dd0133ab7736fc428
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 12:10:07 +02:00
Stefan Reinauer cbb648c001 Enable -Werror for romcc
... and remove some dead code.

Change-Id: Id959bdf57af09db2a1f5742555c2dcabca38ac9a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/818
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 12:07:10 +02:00
zbao d086d51b5e Keep cscope.out when distclean.
It doesnt make sense to delete cscope.out when make
distclean. Distclean is done all the time, and cscope database is also
needed all the time. If we need to delete all the untracked files, we
can use git-clean.

Change-Id: Ic248ccd602ddc88d0b98d5d7f6cbbf530cd82e87
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/831
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 12:06:10 +02:00
Kyösti Mälkki a860c683bc Intel cpus: get MAXPHYADDR at runtime for new CAR
Use CPUID to get MAXPHYADDR and set MTRR masks correctly.
Also only BSP CPU clears MTRRs and initializes its Local APIC.

Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/686
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 12:03:44 +02:00
Kyösti Mälkki 0078ceb553 Intel cpus: add hyper-threading CPU support to new CAR
This improvement of CAR code starts the sibling CPU processors and
clears their cache disable bits (CR0.CD) in case a hyper-threading
CPU is detected.

Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/604
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31 12:02:16 +02:00
Kyösti Mälkki 05d6ffba0f Intel cpus: improve CPU compatibility of new CAR
Most or many Xeons have no MSR 0x11e.

I have previously tested that a HT-enabled P4 (model f25) can
execute this but will not have cache-as-ram enabled. Should work
for non-HT P4.

Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/644
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31 11:58:51 +02:00