Commit Graph

16956 Commits

Author SHA1 Message Date
Vladimir Serbinenko f004b6b927 stout: Support native raminit
Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13660
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 18:03:08 +01:00
Vladimir Serbinenko 144eea0697 Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs.

Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 17:09:05 +01:00
Martin Roth c37c7c8b1f util/kconfig: Ignore extra symbols in configs instead of failing
When updating an old .config file that has a symbol that has been
removed from the current Kconfig tree, kconfig will generate a warning
and fail to save the updated file.  This is incredibly annoying, and
not the goal when trying to eliminate Kconfig warnings.

Instead of generating a warning, just print a message that it's being
ignored.  This will remove the offending symbol, while allowing the
updated config file to be saved.

Split the change from 1 line to 3 lines to keep it at 80 characters.

Change-Id: I09d5775c9ed14bde80077b51b862a7f41bee098a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12 17:03:36 +01:00
Patrick Georgi 5cde0cb0a7 mainboards: Drop remaining references to vboot indexes
Those aren't used anymore.

Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13685
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12 11:07:56 +01:00
Vladimir Serbinenko 4a84e47211 Fix butterfly usb map.
This was copied from mrc structure despite them having fields in different
order.

Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13661
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 09:06:39 +01:00
Stefan Reinauer 0544b31a49 bimgtool: Fix printf warning for off_t
off_t wants to be printed with %zd, not %d.

Change-Id: I3f6e1988bb306f4a7738f1f3ccb2093518e4ceb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13655
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12 04:47:37 +01:00
Stefan Reinauer f0d0d91868 bimgtool: Match CRC code guards
Make sure that the statically defined CRC functions are
enabled by the same conditionals as the code using them.

Change-Id: Ic24e2ed1a80b8e5f6623881b08d86f7b608a206e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13654
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 04:47:20 +01:00
Stefan Reinauer 3740d77020 bimgtool: Drop unused targets and variables from Makefile
dep has not been defined (and will hence break the build)
LDFLAGS is not used.

Change-Id: I4f91e1e7a176367aa4e1a1c63a2afc0b3186767e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13653
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12 04:47:04 +01:00
Vladimir Serbinenko 613d3ad208 Move gpio.h to gpio.c on sandy and ivy.
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13657
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 04:22:00 +01:00
Vladimir Serbinenko ffbb3c0b8a Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 04:20:57 +01:00
Aaron Durbin 622eea7e81 arches: lib: add main_decl.h for main() declaration
It is silly to have a single header to declare the main()
symbol, however some of the arches provided it while
lib/bootblock.c relied on the arch headers to declare it. Just
move the declaration into its own header file and utilize it.

Change-Id: I743b4c286956ae047c17fe46241b699feca73628
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13681
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-11 23:29:08 +01:00
Aaron Durbin 711455f244 arch/{arm64,riscv}: remove jmp_to_elf_entry() declaration
jmp_to_elf_entry() is not defined anywhere. Remove it.

Change-Id: I68f996a735f2ef3dd60cf69f9b72c3f1481cbb55
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11 23:28:52 +01:00
Aaron Durbin ae4b854080 lib/prog_loaders.c: remove arch/stages.h include
There's no delcaration used. Remove the include.

Change-Id: I6fa7de6362ca0e92f0d5a7d07f3a224b9f77f709
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11 23:12:12 +01:00
Aaron Durbin ae3f3024d9 arch: remove stage_exit()
It's no longer used. Remove it.

Change-Id: Id6f4084ab9d671e94f0eee76bf36fad9a174ef14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11 23:12:06 +01:00
Julius Werner 69d20c45ec timestamp: Bump CBMEM timestamp count, make full use of pre-RAM regions
Since we're reaching the timestamp limit on certain platforms (both for
the pre-RAM cache and the final CBMEM region), this patch increases the
amount of space for both. In the pre-RAM case, it achieves this by
always utilizing the full size of the TIMESTAMP() region allocated in
memlayout.ld, rather than arbitrarily limiting it to some constant.

BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that I can once again see all pre-RAM
timestamps after picking in the LZ4 patch series.

Change-Id: Iabb075a48d8d1e3e1811afeaad5ab47e7846c972
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13651
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:05:19 +01:00
Andrey Petrov 87fb1a6cdb soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.

Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 21:16:45 +01:00
Andrey Petrov 57799dcdd1 soc/apollolake: Add minimal GPIO driver
This adds the minimal functionality needed to configure SoC pads.

Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-02-11 21:10:47 +01:00
Alexandru Gagniuc 86f6a135a1 mainboard/intel: Add skeleton for Apollolake RVP board family
RVP1 board comes with DDR3 SODIMMs and discrete VRs.
RVP2 board uses LPDDR3 and PMIC.

Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13298
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 21:10:30 +01:00
Alexandru Gagniuc dfc2b31517 soc/apollolake: Add initial cache-as-ram setup for bootblock
This is the minimum setup needed to both get cache-as-ram setup and a
C environment working. On apollolake, we only get 32 KiB of data
loaded into an SRAM that is readonly to the main CPU. Due to this
restriction we have to set CAR and a C environment very early on.

Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 21:00:07 +01:00
Patrick Georgi 9f428137b7 git modules: rename git submodules to avoid hierarchies
Having a git module named "3rdparty" and another one in
"3rdparty/chrome-ec" led to git failures when the latter was initialized
before the former (because of git being stupid, but then it says so on
the box, right?)

Rename modules so there's no such hierarchy (3rdparty ->
3rdparty/blobs). While at it, also rename the culprit to match the path
name (3rdparty/chrome-ec to 3rdparty/chromeec).

git will resolve this on the next git submodule update invocation (eg.
the next coreboot build).

Change-Id: Ief79074d73abeefff36a47b2e58ac6b1c047e3a7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13675
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2016-02-11 20:55:55 +01:00
Patrick Georgi 1509c908aa 3rdparty/chromeec: fix build with paths containing "@"
Move submodule forward to a newer upstream master to fix the build on
paths containing "@", as can happen on jenkins.

Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13673
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11 20:52:26 +01:00
Alexandru Gagniuc 0492c8cf26 cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well
This is needed in a follow-on patch to enable udelay() handling on
apollolake, which is a dependency for the console code.

Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 19:21:24 +01:00
Ruilin Hao c52d4f5745 util/marvell: Add Marvell doimage utility and dependency in relevant Makefile
- Add the doimage sources in util/marvell
- Add dependency in root makefile
- Add dependency in makefile for armada38x soc

BUG=chrome-os-partner:47462
TEST=emerge-cyclone coreboot
BRANCH=tot

Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab
Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9
Original-Signed-off-by: Kefei Yao <kfyao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/318046
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org>
Reviewed-on: https://review.coreboot.org/13137
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-11 14:16:08 +01:00
Andrey Petrov 3bc543a5c3 arch/x86: Change how BOOTBLOCK_CUSTOM is selected by default
Currently x86s select BOOTBLOCK_CUSTOM by default. With this
change BOOTBLOCK_CUSTOM is selected only if C bootblock isn't.

Change-Id: I218f3b4044175b89697790c82c384b0f85a27ade
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13642
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 06:22:08 +01:00
Andrey Petrov 6a1219cfe0 arch/x86: Allow bootblock code to use CAR_GLOBAL variables
Since cbmem is not initialized in bootblock, CAR_GLOBAL variables
can only be accessed directly similar to verstage.

Change-Id: Ifc705016290807c49dc8c49b581864cac2ad3f80
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 06:21:58 +01:00
Andrey Petrov ee9e4ae5bf arch/x86: Reserve space for stack in CAR layout
Some platforms may want to use C code in bootblock so they need
writable memory and CAR can be used for it. This change reserves
memory in CAR that can be used by bootblock and other CAR stages.

Change-Id: I8dec768cf8763dbe235f0ba1339079ebc49cbd9a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13640
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 06:21:46 +01:00
Aaron Durbin a02bb653fd cpu/intel/microcode: allow microcode to be loaded in romstage
The previous usage of the intel microcode support supported using
the library under ROMCC and ramstage. Allow for microcode support
to be used in normal C-based romstage as well by:

1. Only using walkcbfs when ROMCC is defined.
2. Only using spinlocks if !__PRE_RAM__

The header file now unconditionally exposes the declarations
of the supporting functions.

Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10 18:08:28 +01:00
Martin Roth 5a70d6bdf2 kconfig_lint: update kconfig lint shell scripts
- Add lint-stable script with just error checking
- Enable warnings in addition to errors in non-stable test.
- Use git grep if the code is in a git repo now that exclusions are
working.
- Check for perl, and ask the user to install it if it isn't
available.

Change-Id: Ie60d21f4ef8a61d879f116eb2056eb805b0a55f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13542
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-02-10 17:17:56 +01:00
Martin Roth 9e620eaff4 chromeos/Kconfig: Remove dependency on GBB_HAVE_BMPFV
This symbol is not defined.

Change-Id: I2b0a3fca82d85962fc882f237b70702cab0400db
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/13647
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-10 16:53:55 +01:00
Martin Roth 59ff3400b0 Kconfig: Move defaults for CBFS_SIZE
We want the question for CBFS size to be next to the rom size in the
mainboard directory, but that doesn't seem to work for how people
want to set the defaults.  Instead of having the list of exceptions
to the size, just set the defaults at the end of kconfig.

- Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into
the chipset Kconfigs (gm45, nehalem, sandybridge, x4x)
- Override the default for HAVE_INTEL_FIRMWARE on skylake.
- Move the HAVE_INTEL_FIRMWARE default setting into the firmware
Kconfig file
- Move the location of the default CBFS_SIZE=ROM_SIZE to the end of
the top level kconfig file, while leaving the question where it is.

Test=rebuild Kconfig files before and after the change, verify that
they are how they were intended to be.

Note: the Skylake boards actually changed value, because they were
picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the
0x200000 desired.  This was due to the SOC_INTEL_SKYLAKE being after
the HAVE_INTEL_FIRMWARE default.  Affected boards were:
Google chell, glados, & lars and Intel kunimitsu.

Change-Id: I2963a7a7eab037955558d401f5573533674a664f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10 16:27:50 +01:00
Ben Gardner a3e4833e5d intel/fsp1_0: Allow the MRC cache to live in a FMAP region
The new option CONFIG_MRC_CACHE_FMAP will cause fastboot_cache.c to
look in the FMAP for a region named "RW_MRC_CACHE" and prevents adding
a CBFS file named "mrc.cache".

Tested on a fsp_baytail-based board.

Change-Id: I248f469c7e3447ac4ec7be32229fbb5584cfd2ed
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13632
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10 16:27:12 +01:00
Patrick Georgi b19425b46b google/veyron_speedy: remove extraneous file
veyron_speedy was deduplicated as sub-board into google/veyron, so the
addition of chromeos.fmd (identical btw) wasn't useful.

Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10 15:04:47 +01:00
Patrick Georgi 6b881b24a3 google/chromeos: backup -> back up
See discussion on https://review.coreboot.org/13600 and
https://review.coreboot.org/13601

Change-Id: Ia8274b0b296d6b398f75c0d91a6fded4c5f57e10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13643
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10 15:04:23 +01:00
Patrick Georgi aaa3b4a0d7 gitconfig: Fix make gitconfig if USE_BLOBS is disabled
We tested for the presence of .git/modules/3rdparty, which always exists
now because of .git/modules/3rdparty/chrome-ec. Test for .../hooks
instead since that's the actual location for the later activities.

Change-Id: Id5de9f850413c2bc3525faa6cc549641304c3d47
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13650
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 09:46:22 +01:00
Patrick Georgi 8e68aff51c buildgcc: enable multilib for gcc
Make the gcc build system create multiple libgcc.a instances for
different ABIs.

Change-Id: I1c888bf751bf43566da8927ed0aedb53857363bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 09:45:58 +01:00
Julius Werner 3834520ba1 arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload
The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts
and Fast interrupts are usually best left unset: under normal
circumstances none of those exceptions should occur in firmware, and if
they do it's better to get a crash close to the code that caused it
(rather than much later when the kernel first unmasks them). For this
reason arm64_cpu_init unmasks them right after boot. However, the EL2
payload was still running with all mask bits set, which this patch
fixes.

BL31, on the other hand, explicitly wants to be entered with all masks
set (see calling convention in docs/firmware-design.md), which we had
previously not been doing. It doesn't seem to make a difference at the
moment, but since it's explicitly specified we should probably comply.

BRANCH=None
BUG=None
TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask
bits are now cleared.

Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8
Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 09:39:36 +01:00
Julius Werner 372d0ff1d1 arch/arm64: mmu: Spot check TTB memory attributes
On ARM64, the memory type for accessing page table descriptors during
address translation is governed by the Translation Control Register
(TCR). When the MMU code accesses the same descriptors to change page
mappings, it uses the standard memory type rules (defined by the page
table descriptor for the page that contains that table, or 'device' if
the MMU is off).

Accessing the same memory with different memory types can lead to all
kinds of fun and hard to debug effects. In particular, if the TCR says
"cacheable" and the page tables say "uncacheable", page table walks will
pull stale entries into the cache and later mmu_config_range() calls
will write directly to memory, bypassing those cache lines. This means
the translations will not get updated even after a TLB flush, and later
cache flushes/evictions may write the stale entries back to memory.

Since page table configuration is currently always done from SoC code,
we can't generally ensure that the TTB is always mapped as cacheable.
We can however save developers of future SoCs a lot of headaches and
time by spot checking the attributes when the MMU gets enabled, as this
patch does.

BRANCH=None
BUG=None
TEST=Booted Oak. Manually tested get_pte() with a few addresses.

Change-Id: I3afd29dece848c4b5f759ce2f00ca2b7433374da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3947f4bb0abf4466006d5e3a962bbcb8919b12d
Original-Change-Id: I1008883e5ed4cc37d30cae5777a60287d3d01af0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323862
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 09:39:23 +01:00
Lee Leahy 89c61b5630 soc/intel/quark: Report CPU info
Decode the CPU variants and display the CPU info.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Successful if Quark X1000 is displayed

Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13605
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10 03:12:18 +01:00
Lee Leahy d4edacb2e4 soc/intel/quark: Call FSP SiliconInit
Optionally relocate FSP into DRAM and then call FSP SiliconInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_FSP_ENTRY_POINTS"
   *  Add "select DISPLAY_HOBS"
   *  Optionally add "select RELOCATE_FSP_INTO_DRAM"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  FSP entry points are displayed and
   *  The message "FspSiliconInit returned 0x00000000" is displayed and
   *  The HOBs are displayed correctly and
   *  The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed

Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13631
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10 03:12:10 +01:00
Lee Leahy 43cdff6b45 soc/intel/quark: MTRR support
Add the SoC specific routines to access the MTRR registers.  These
registers exist in the host bridge and are not accessible via the
rdmsr/wrmsr instructions.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_MTRRS"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  The message "FSP TempRamInit successful" is displayed

Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13530
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10 03:11:45 +01:00
Ben Gardner 3968653f25 soc/fsp_baytrail: Add support for FSP MR 005
Baytrail FSP MR 005 adds two new fields:
  AutoSelfRefreshEnable
  APTaskTimeoutCnt

Add the device tree definitions.

Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12973
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10 02:45:56 +01:00
Lee Leahy 318ef96af3 soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_HOBS"
   *  Add "select DISPLAY_UPD_DATA"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
    CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  MemoryInit returns 0 (success) and
   *  The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed

Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13447
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 02:42:21 +01:00
Vladimir Serbinenko c285b30b7d ASL: Remove unused modulo recipient.
Change-Id: I4b0a3073815ec8d98c2d23cd745f027517b6fa42
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13619
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 22:56:00 +01:00
Vladimir Serbinenko 93fc60621c stout: Add native gfx init
Tested during FOSDEM.

Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13532
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 22:35:23 +01:00
Vladimir Serbinenko b2eea81992 sandybridge: Set all native gfx-related options in northbridge code.
In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.

Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-09 22:35:09 +01:00
Martin Roth f80331f261 SeaBIOS: Disable serial console if serial is memory mapped
SeaBIOS only supports standard IO based serial ports.  If the serial
port being used by coreboot isn't a standard IO serial port, disable
the serial console in the SeaBIOS build.

Change-Id: I386b46625fca0bd0a5416ed9831f8370c294ed74
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13617
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09 22:31:12 +01:00
Patrick Georgi d4adf58e03 libpayload: use 32bit access when accessing 4byte wide uart registers
This fixes serial on rk3288.

Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13636
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-02-09 21:53:42 +01:00
Patrick Georgi 42636a7a0c rockchip/rk3288: UART uses 32bit wide registers
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13635
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09 21:53:22 +01:00
Martin Roth 15f4d8c1bb kconfig_lint: demote 'always defined' errors to warnings
To be able to run this as a lint-stable test, demote these to warnings
for now.  After the current CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
issues get fixed, these can be promoted again.

Change-Id: I1432980eb0c871fc61c12dcc351f8d46513a7965
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13541
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09 21:52:45 +01:00
Patrick Georgi eda794d2cc vboot2: Store depthcharge graphic assets only in RO
These files aren't updated (or updatable), and as such don't need to be
copied to the RW sections.

Change-Id: Ie78936792ad651fbf8500fc7e34f0899e33a904c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09 21:52:05 +01:00