Commit graph

59 commits

Author SHA1 Message Date
Elyes HAOUAS
90d00dea55 {src/mb,util/autoport}: Use macro for DSDT revision
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13 18:27:04 +00:00
Furquan Shaikh
a266d1e63a mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.

BUG=b:169802515
BRANCH=zork

Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13 17:38:38 +00:00
Subrata Banik
6577ec4de4 soc/intel/common/block/acpi: Factor out common platform.asl
This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:01:40 +00:00
Michael Niewöhner
87cc889e8b treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFS
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is
used for, so rename it to HAVE_SPD_BIN_IN_CBFS.

Change-Id: I4004c48da205949e05101039abd4cf32666787df
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 09:00:47 +00:00
Michael Niewöhner
702e60ad8a mb/system76/lemp9: gpio: convert gpio.h to a cleaner format
Convert gpio.h to a compacter, cleaner format by keeping gpios in a
single line, where possible.

This was done with the following fancy vim regex replacement commands.
(Neither sed, nor awk multiline matching syntax are friends with me...)
Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before
pasting each command, press enter and see how the format changes.

g#^\t//#d
%s/^\t\t/\t/
g/PAD_.*$\n\n[^/]/s/\n//
g#// NC#d
%s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g
%s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */
%s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */#

Finally some indents and multiline comments need to be fixed manually.

Test: images built with TIMELESS do not differ.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-09-22 20:06:03 +00:00
Michael Niewöhner
4c0cea2147 mb/system76/lemp9: convert inverted SCI/SMI macros to _LOW macro
Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which
is better understandable.

Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22 17:35:18 +00:00
Michael Niewöhner
e4031c558d mb/system76/lemp9: gpio: convert the remaining raw pads to macros
Convert the EC and touchpad interrupt pads from raw to macros. This
was done with intelp2m.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 23:52:21 +00:00
Michael Niewöhner
3f5bfbd4d1 mb/system76/lemp9: move LPC options to the devicetree
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 21:32:50 +00:00
Michael Niewöhner
80bd8e43b0 mb/system76/lemp9: correct CBFS_SIZE
The BIOS region size is 0xc00000, not 0xa00000. Correct this.

Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-09-20 21:32:32 +00:00
Michael Niewöhner
8b5cd49b5a mb/system76/lemp9: enable SATA ALPM capability
Enable SATA Link Power Management capability to be able to save power.

TEST: /sys/class/scsi_host/host*/link_power_management_policy exists.

Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 21:32:21 +00:00
Michael Niewöhner
c9ebf8d501 mb/system76/lemp9: drop disabled options from devicetree
Drop all options with zero-value, since they already default to 0.

Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 21:32:11 +00:00
Michael Niewöhner
5a85d134b1 mb/system76/lemp9: move subsystem id from Kconfig to devicetree
Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19 16:46:54 +00:00
Jeremy Soller
b349f258a9 mb/system76/lemp9: update power limits
Tested on lemp9, power limits are adjusted from the previously low
values to the values the thermal system can handle. This was
determined by increasing the values and running the system at 100%
CPU utilization until thermal throttling occured and the chassis
temperature became uncomfortable.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I5e176e9d98376f8e2dc415e4397efc456869e72d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43624
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 21:37:11 +00:00
Michael Niewöhner
d7775b763f mb/system76/lemp9: disable PCH DMIC, which is not wired
The microphone is wired to the audio codec, not to the PCH. Disable the
DMIC interface.

Change-Id: I4128a694c1a66d3c2c2d1cb831fcca3487160f8f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45133
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 21:35:32 +00:00
Jeremy Soller
748bfac734 mb/system76/lemp9: skip FSP init of UART2
This UART is already initialized by coreboot for the console, it does
not need to be initialized by the FSP.

Tested on lemp9.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I7c299fd7cf6fe53d1f500a899a14e63e51ad6266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-17 20:47:49 +00:00
Michael Niewöhner
1d7b7f6e7a mb/system76/lemp9: move HDA options into devicetree
Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45132
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:24:30 +00:00
Jeremy Soller
27dd66aca7 mb/system76/lemp9: update HDA pin config
To minimize the quirks the kernel has to apply, the headset mic is set
to its correct value in coreboot.

Tested on lemp9, audio is functional.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43631
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:35:56 +00:00
Felix Singer
7e396f380e mb/system76/lemp9: Add SMBIOS descriptions to root ports
Change-Id: Ie663d424edbbeeb8f5691b00f3977f7501e9ab45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 21:35:29 +00:00
Felix Singer
be50ab0878 mb/system76/lemp9: Move PCIe root port config into devicetree
Change-Id: Idd38ab530fd8a0c16231f3499eac393c333a9a92
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 21:27:20 +00:00
Felix Singer
1a8c0defd7 mb/system76/lemp9: Add comments to SATA ports
Change-Id: I8db3bfbdb557a84413408b4b39a13b24c45497cc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 20:09:34 +00:00
Felix Singer
f0a8850259 mb/system76/lemp9: Move USB options into devicetree
Change-Id: I3371bed7c2678fbc3304f53af1413a93462933f5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 20:08:43 +00:00
Felix Singer
4ca3873457 mb/system76/lemp9: Enable SataPortsDevSlp
Enable SataPortsDevSlp for SATA ports 2 and 3.

Change-Id: Id6c69f4a6fe45cb5c6aad3f42c741a2724c6166c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 12:32:58 +00:00
Felix Singer
63b9e791bc mb/system76/lemp9: Move SATA options into devicetree
Change-Id: Idf64d98b36ca95a8bc17a6544993c26e23851cd8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 12:31:52 +00:00
Felix Singer
23cf3391ed mb/system76/lemp9: Don't configure unused SATA / USB ports
Change-Id: Ic5587402700d7b137e20538549b8a09a64cb6a9f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-07 12:30:39 +00:00
Jeremy Soller
2d28c4cff4 mb/system76/lemp9: enable I2C HID touchpad
Enable the I2C HID driver, configure I2C bus 0 and add the touchpad
device to the devicetree.

Tested on lemp9, touchpad confirmed to use i2c-hid driver in Linux
instead of PS/2.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Ic3a90fda134b1d53f28ab687b3033ec52fee843b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43623
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06 16:37:03 +00:00
Jeremy Soller
f0eb1925e4 mb/system76/lemp9: Use absolute path for _GPE
_GPE cannot be anywhere but at the root of the ACPI namespace.

This change ensures that is always the case.

Tested on lemp9, GPE still in correct location.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Ib31683b06e61da4b1859cd939c36879cebf4c03c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43630
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06 14:41:54 +00:00
Jeremy Soller
592b0ad3ef mb/system76/lemp9: Drop DeepSx settings
The GPIOs required for DeepSx (e.g. SLP_SUS#) are not hooked up on the
lemp9. Therefore, drop the DeepSx settings.

Tested on lemp9, suspend works correctly.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Iab179abd7adc3a65dcfc43ce1b5742d514b711fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43629
Reviewed-by: Michael Niewöhner
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06 14:41:08 +00:00
Jeremy Soller
41e9ad6564 mb/system76/lemp9: Enable SA thermal device
Tested on lemp9, SA thermal device appears in lspci.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I527e586b1dae5f8087d2364c63c9db5bcb643214
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner
2020-09-06 14:40:48 +00:00
Felix Singer
1f5a34454d mb/system76/lemp9: Don't enable unused USB3 port
Don't configure USB3 port 4 since it's not used.

Change-Id: I6919f5ec3a5be53373f2ab75063764287b53baf5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Michael Niewöhner
2020-09-05 08:55:44 +00:00
Felix Singer
d9e459428d soc/intel/cnl: Enable HECI3 depending on devicetree
Currently HECI3 gets enabled by the option Heci3Enabled, but this
duplicates the devicetree on/off options. Therefore depend on the
devicetree for enablement of the HECI3 controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Heci3Enabled setting, and divergent
devicetrees were adjusted.

Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-04 11:50:30 +00:00
Felix Singer
e1af5b8d26 soc/intel/cnl: Add new Kconfig option which matches its FSPs name
Since there are 4 different versions of FSPs for the Comet Lake
platform, add a new Kconfig option for the currently used SoC being able
to differ between the various SoCs and FSPs.

The new Kconfig option selects the Comet Lake SoC as base for taking
over its specific configuration and is only used for configuring the
path to its specific FSP header files and FSP binary.

Also, adjust all related mainboards so that their Kconfig selects the
new option.

For details, please see
https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg

Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch
and both images are equal.

Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-03 21:04:57 +00:00
Elyes HAOUAS
b56d596905 mb/*/Kconfig: Drop redundant 'select DRIVERS_INTEL_WIFI'
DRIVERS_INTEL_WIFI is already set to yes.

Change-Id: I09f628a9c1feb8992b6fe7c7ca93c75243ffc0f1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-02 13:40:46 +00:00
Elyes HAOUAS
53b0f14b70 mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES'
GENERATE_SMBIOS_TABLES is already set to yes at src/Kconfig

Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-09-02 07:16:28 +00:00
Michael Niewöhner
1c97793b79 mb/system76/lemp9: gpio: add a pull-down for MODEM_CLKREQ / CNVI_CLKREQ
MODEM_CLKREQ / CNVI_CLKREQ has no external pull-down resistor.
When there is no M.2 card populated, the pin is floating. Thus
enable an internal 20K PD.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I37e0a9d7e9e0a8c8a7ac198abfd3995b8b0f9e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-08-30 23:13:47 +00:00
Michael Niewöhner
8e2101d438 mb/system76/lemp9: add wifi devices
Add CNVi and PCIe wifi devices to the devicetree and enable the wifi
driver and SMBIOS tables in Kconfig.

Test: both CNVi and PCIe wifi devices work fine

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I16e04dbbf5fc3a163ce5a2bb8de646877d5cbc0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43654
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:59:35 +00:00
Michael Niewöhner
47fd4fa617 mb/system76/lemp9: gpio: rework comments
Rework the comments:
  - fix wrong gpio / net names
  - convert all comments to <gpio> / <net name>
  - add more information where appropriate

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:56:58 +00:00
Michael Niewöhner
90041ef886 mb/system76/lemp9: gpio: convert PAD_CFG_TERM_GPO to PAD_CFG_GPO
Convert PAD_CFG_TERM_GPO with pull "NONE" to its shorter equivalent
PAD_CFG_GPO.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9ed4d97ba184fa3e72425d5d16042a142b0640b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43649
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:55:43 +00:00
Michael Niewöhner
dd70d28ef7 mb/system76/lemp9: gpio: disable unused pad for INTP_OUT
INTP_OUT can be used as Type-C VBUS sense input/interrupt but is
currently unused in coreboot. It isn't a requirement for PD to work.
Disable it for now.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:52:10 +00:00
Michael Niewöhner
78cb41798e mb/system76/lemp9: gpio: disable internal SATAXPCIE pull-ups
Disable internal pull-ups for SATAXPCIE pads since there are external
ones at the M.2 slot's PEDET pins.

Test: both, SATA and NVME devices work fine on both slots

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:51:54 +00:00
Michael Niewöhner
1ba8a50df3 mb/system76/lemp9: gpio: configure unused pads
There are pads being unused for various reasons:
  a) missing board support (DeepSx: SUSWARN#)
  b) unneeded feature ID pins
     - currently no known device models without keyboard backlight
     - currently no known device models without TPM
  c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time
  d) DDR_TYPE_*: there is only one known ram model
  e) strap-only pads
  f) unconnected pads

Configure them as NC with appropriate pull-up if no external pull exists.
The latter was checked by schematics and looking at the board.

When any of the unused ID pins is needed in the future, they can be
reactivated easily (configure as GPI).

Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:51:34 +00:00
Michael Niewöhner
f0b6b30c46 mb/system76/lemp9: enable TPM
L140CU has a TPM2 connected via SPI. Add the TPM device to the
devicetree and enable it.

According to Intel doc#615170-001, PIRQ is required for SPI TPM to work.
Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as
TPM interrupt in Kconfig.

Note: The PCH maps either LPC TPM or SPI TPM to the same address and
handles either LPC or SPI communication transparently. Thus we can use
MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address.

Tested, but only polling works currently, because there is some upstream
issue with the tpm_tis module in current Linux kernels. [1]

[1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 21:10:13 +00:00
Nico Huber
119ace0908 soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-23 09:57:02 +00:00
Felix Singer
3de90d1344 soc/intel/cnl: Set Heci1Disable depending on devicetree config
Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.

All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.

Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-07 20:35:29 +00:00
Felix Singer
1f10db2828 mb/system76/lemp9: Relocate device enable options
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.

Change-Id: I655bc7576e8ff48258a2a19387e01372f4bbea3d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-28 09:46:07 +00:00
Jeremy Soller
0de0fe1104 ec/system76_ec: add support for System76 EC
This adds ACPI code for System76 EC and converts system76/lemp9
to use EC_SYSTEM76_EC.

Tested on system76/lemp9.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-23 09:30:22 +00:00
Michael Niewöhner
48833363da mb/system76/lemp9: drop FSP_M_XIP
Drop FSP_M_XIP since it's selected by the soc already.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I999d369be395de08d4ab7f115fedf4b7fa10eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-07-21 22:11:56 +00:00
Michael Niewöhner
f662020a4d mb/system76/lemp9: drop ONBOARD_VGA_IS_PRIMARY
Drop config ONBOARD_VGA_IS_PRIMARY as it's only needed for mainboards
with multiple graphics devices.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6525c65af3dcfc96ea3d68a1388432179e9ac43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43636
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 22:11:41 +00:00
Patrick Georgi
3588d7b76f mb/*/*/Kconfig: guard board name in quotes
New kconfig dislikes unquoted slashes.

Change-Id: Ief242de081071021b9c904a24535d025f6674270
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19 15:28:48 +00:00
Sumeet R Pawnikar
309ccf74dd cannonlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Cannonlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on drallion system

Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26 15:02:54 +00:00
Nico Huber
9ea70c02cd intel/cannonlake: Implement PCIe RP devicetree update
Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.

Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 15:01:00 +00:00