GNUBoot/coreboot-kgpe-d16
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514 commits

Author SHA1 Message Date
Aamir Bohra
3b1a42f95d mb/google/hatch: Enable LPC/eSPI controller 
Enable LPC/eSPI controller(D31:F0). EC would be using
eSPI interface, since the strap GPP_C5 is pulled up.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2018-12-28 06:38:10 +00:00
Aamir Bohra
049ad67f76 mb/google/hatch: Add SMI handlers 
Add SMI handlers for below SMI events:

1. eSPI SMI event.
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep(S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-27 22:08:57 +00:00
Maulik V Vaghela
04a7ce728d mb/google/hatch: Add HPD GPIO support for displays 
Adding hot plug detect GPIO support for external Type-C display in event for
cable connect/disconnect.

Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30365
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-25 03:44:11 +00:00
V Sowmya
656015c258 mb/google/hatch: Modify hatch SPI flash layout 
This patch modifies the hatch flash layout to support
IFWI 1.6 with the following regions,
Flash Region 0: Descriptor
		[0x0 - 0xFFF]
Flash Region 1: IFWI (consist of ME and PMC FW)
		[0x1000 - 0x3FFFFF]
Flash Region 2: BIOS
		[0x1400000 - 0x1FFFFFF]

Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30413
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-25 03:43:34 +00:00
Aamir Bohra
6aaae1c893 mb/google/hatch: Enable EC LPC interface and configure IO decode range 
Enable EC LPC interface and configure below LPC IO decode ranges:

1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-25 03:42:59 +00:00
Aamir Bohra
0dfda74408 mb/google/hatch: Add SoC and EC asl files in DSDT 
This implementation adds below code:

1. Add SOC ACPI code in dsdt.asl
   -> platform.asl
   -> globalnvs.asl
   -> cpu.asl
   -> northbridge.asl
   -> southbridge.asl
   -> sleepstate.asl

2. Add chromeos.asl in dsdt.asl

3. Add EC ACPI code in dsdt.asl
   -> superio.asl
   -> ec.asl

4. Remove config for WAK/PTS ACPI method as chromeec
   doesn't implement those.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-25 03:42:23 +00:00
Aamir Bohra
3a167f56f4 mb/google/hatch: Add EC trigger events and acpi configs 
This implemetation adds EC SCI, SMI, S5/S3 wake trigger events.
Also adds the EC specific ACPI configs to enable support for ALS,
EC PD device and PS2 keyboard device.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: I3a86f609c269cb59e546fc7ba4ba032e5ea8341a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-25 03:41:46 +00:00
Maulik V Vaghela
2fe81b2810 mb/google/hatch: Enable IGD (Integrated GFX Device) 
This patch ensures following 2 features
1. Enable IGD controller in devicetree.cb
2. Pass required FSP UPD to perform internal graphics initialization

Change-Id: I607199590d793a70e1e20bb3241fc34467aa829d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-23 05:12:52 +00:00
Aamir Bohra
4b85d46170 mb/google/hatch: Add memory init setup for hatch 
This implementation adds below support:

1. Add support to read memory strap.
2. Add support to configure below memory parameters
   -> rcomp resistor configuration
   -> dqs mapping
   -> ect and ca vref config
3. Include SPD configuration

BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot

Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-23 05:12:14 +00:00
Shelley Chen
09e7b99837 mb/google/hatch: Enable Elan Trackpad 
BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc" emerge-hatch coreboot

Change-Id: I91db5745d1db16ab4b2fbb7f8c415bd7c1eb29e9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-22 12:14:39 +00:00
Shelley Chen
6bb563f29c mb/google/hatch: Fixes to initial hatch mainboard checkin 
Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.

Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB

BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v

Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30296
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-22 12:14:20 +00:00
Aamir Bohra
6d8e0cdeab mb/google/hatch: Enable H1 TPM support over SPI interface 
Add code support to enable H1 TPM interfaced to SOC on GSPI0.
The TPM interrupt is mapped to GPP_C21.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30210
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-21 04:42:33 +00:00
Aamir Bohra
368598198d mb/google/hatch: Clean up gpio definitions in hatch variant 
This implementation cleans up gpio configuration functions
and limit definition to baseboard only for now, until variant
specfic overides are needed.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-21 04:40:28 +00:00
Shelley Chen
e3110b8620 mb/google/hatch: Creating skeleton directories and files 
Creating skeleton files and directories in mainboard for the new Hatch
board.  This is to facilitate development for different parties
involved.

BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
 2018-12-13 00:46:09 +00:00