Commit Graph

42859 Commits

Author SHA1 Message Date
Tim Wawrzynczak c657ab9750 soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
Add a new function to fill out the data structures necessary to generate
a _PRT table.

BUG=b:130217151, b:171580862, b:176858827

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51159
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 21:51:20 +00:00
Tim Wawrzynczak b59980b54e soc/intel/common: Add new IRQ module
The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if
the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of
rules that the input IRQ table must conform to:
1) One entry per slot/function
2) Functions using PIRQs must use IOxAPIC IRQs 16-23
3) Single-function devices must use INTA
4) Each slot must have consistent INTx<->PIRQy mappings
5) Some functions have special interrupt pin requirements
6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN)
7) Some functions require a unique IRQ number
8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes
   its IRQ through IO-APIC.

Since the FSP has no visibility into the actual GPIOs used on the board
when GpioOverride is selected, IRQ conflicts can occur between PCI
devices and GPIOs. This patch gives SoC code the ability to generate a
table of PCI IRQs that will meet the BWG/FSP rules and also not conflict
with GPIO IRQs.

BUG=b:130217151, b:171580862, b:176858827
TEST=Boot with patch series on volteer, verify IO-APIC IRQs in
`/proc/interrupts` match what is expected. No `GSI INT` or
`could not derive routing` messages seen in `dmesg` output.
Verified TPM, touchpad, touchscreen IRQs all function as expected.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 21:50:45 +00:00
Tim Wawrzynczak ef16df2782 southbridge/intel/common: Move invalid PIRQ value to 0
This makes structs that contain an `enum pirq` field that is
default-initialized have the value PIRQ_INVALID

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 21:50:35 +00:00
Martin Roth bdba51208a mb/google/guybrush: Initialize WWAN for USB if requested
To set the Fibocom 850-GL module to USB mode, it needs to be disabled
when PCIe training happens, or it will automatically switch to PCIe
mode.  This patch makes sure it's shut down when training happens in
FSP-M.  It will be brought up in ramstage and will be available for USB
enumeration later.

BUG=b:187316460
TEST=Run lsusb from the OS and see that the Fibocom module is present
on USB.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29 18:06:30 +00:00
Martin Roth 3360862687 mb/google/guybrush: Update romstage power-on timings for PCIe
This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.

The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.

BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections.  All available modules
are present after training.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 18:06:13 +00:00
Martin Roth 324cea9d1b mb/google/guybrush: Update bootblock power-on timings for PCIe
This configures the bootblock portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.

Setting the PCIE Reset happens in coreboot instead of in the FSP.

The Aux reset lines are anded with the PCIe RST line, so both have
to be brought up together.  On v1 of guybrush, the PCIe reset line
also resets EC communication, so it must be brought up immediately on
that version.

BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections.  All available modules
are present after training.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29 18:06:00 +00:00
Patrick Georgi 46bee3f48c Kconfig: Escape variables
New kconfig parsers interpret $(var) themselves, leading to empty
fields. Old kconfig understands \$(var), so use that.

Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 16:56:45 +00:00
Shelley Chen 8790b9a083 mb/google/herobrine: Add Senor and Piglin variants
Add configs for Herobrine variants.  Also enable ec sw sync as this
should not be disabled by default.

BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B
     ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B

Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-29 16:37:35 +00:00
Pratik Vishwakarma 56731154a6 mb/google/guybrush: provide full range backlight settings to kernel
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide
full range backlight settings to the kernel.

BUG=b:190443612

Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29 15:39:24 +00:00
Varshit B Pandya bee9d6028e mb/google/brya0: Enable MIPI UFC
1. Add 2 port 2 endpoint
2. Add support for OVTI5675
3. Guard entries in override device tree by FW_CONFIG

MIPI UFC is on I2C2
This configuration is as per P2 schematics

BUG=b:190674542
TEST=Build and Boot on Brya

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-29 14:39:49 +00:00
Martin Roth 53435eac51 mb/google/guybrush: Configure eSPI requirements before setting it up
When initializing eSPI early, guybrush has requirements to configure the
bus properly.  Those are normally run in bootblock_mainboard_early_init,
but when setting up eSPI early, those have not run yet.

BUG=192100564
TEST=Build along with previous patch, eSPI works on guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 17:12:02 +00:00
Martin Roth fe58977e6f soc/amd/cezanne: Add call to mb to configure eSPI requirements
When initializing espi early, there may be mainboard requirements to
configure the bus properly.  This allows the mainboard to do that.

BUG=192100564
TEST=Build along with next patch, eSPI works on guybrush

Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-28 15:57:26 +00:00
Sheng-Liang Pan 5a3b07d168 mb/google/volteer/var/volet: add G2 touch support
Enable G2 touchscreen support for Volet.

BUG=b:185097280
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I907356448b5d5cbf3974717654ea09cd995962f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55835
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 15:35:07 +00:00
Zanxi Chen 1c43d92efc mb/google/dedede/var/blipper: Update devicetree and gpio setting
To reduce power load, set unused GPIOs to NC and close
unused interface in devicetree. GPIOs and
interfaces are as below:
GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07
Interface: I2C1/I2C3/I2C5
USB: port2_3/2_4/2_6

BUG=b:185044041
BRANCH=dedede
TEST=Built bios and test, it reduces power load without affecting
device function.

Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
2021-06-28 06:01:24 +00:00
Varshit B Pandya 70d0795df9 mb/google/brya0: Add FW_CONFIG for UFC
UFC on brya can be USB or MIPI
Add FW_CONFIG bit for this option

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-28 06:00:30 +00:00
Maulik V Vaghela 9e23d017f5 mb/google/brya: Update mainboard properties for BB retimer upgrade
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.

Reference CB:54292

BUG=b:186521258
TEST=Updated BB retimer FW from 3.4 to 3.5 without any device
connected.

Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28 04:33:04 +00:00
Tao Xia b34950e68a mb/google/dedede/var/sasukette: Update DPTF parameters
Update DPTF parameters from internal thermal team.

BUG=b:180875580
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28 04:30:25 +00:00
Nikolai Vyssotski 63e98fc209 src/device/dram: Add terminating new lines to printk strings
BUG=b:184124605
TEST=check serial log

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I521a2541e23d047e255b0cc8068ad63dfaf70bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-28 04:29:57 +00:00
Dtrain Hsu d3230b5f70 mb/google/dedede/var/cret: Add ssfc codec cs42l42 support
Add cs42l42 codec support in cret.

BUG=b:188623237, b:189073353
TEST=Build and boot to check functional with cs42l42 EV board.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2c53291e07fd785c1360c05171eed634788bc665
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 04:29:30 +00:00
Bernardo Perez Priego 43fd040226 mb/intel/adlrvp_m: Enable TCSS USB ports device path
This provide a more consistent mechanism to enable corresponding USB
TCSS port.

BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 04:26:53 +00:00
Alex1 Kao fa6d31f999 mb/google/dedede/var/pirika: Update DPTF parameters
Update DPTF parameters from internal thermal team.

BUG=b:190518303
BRANCH=None
TEST=emerge-dedede coreboot

Change-Id: I4005047e0c5f39a12c161a92fbd0afaaec1dc976
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28 04:25:47 +00:00
Arthur Heymans bf4a8d6372 security/intel/cbnt: Fix logging
The wrong format was used. It looks like struct bitfields are of type
int according to gcc so %u needs to be used and not %lu.

Change-Id: I54419d722aec0d43e6f54a4bb4eb4d899c909fec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 04:25:23 +00:00
Alex1 Kao 483880e225 mb/google/dedede/var/pirika: Support audio AMP auto mode
Support audio AMP selection with fw_config.

BUG=b:188446060
BRANCH=None.
TEST=built pass

Change-Id: Idf0eb2a87bfa9665e61d185e37adb90987f3cefb
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28 04:24:37 +00:00
Zanxi Chen d6b34b39f8 mb/google/dedede/var/blipper: Enable ELAN touchscreen
Modify driver from hid to generic(ELAN0001 that used
generic driver without hid).

BUG=b:191620724
BRANCH=dedede
TEST=build bios and boot, touchscreen will work properly.

Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
2021-06-28 04:23:13 +00:00
Angel Pons f585c6eeea soc/intel: Drop casts around `soc_read_pmc_base()`
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a54 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.

Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-28 04:16:48 +00:00
Arthur Heymans c44ffc3084 security/intel/cbnt: Build test CBnT provisioning
This updates the intel-sec-tools submodule pointer to include a fake
acm binary to be included for buildtesting.

Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-28 04:13:54 +00:00
Johnny Lin c05aa26a1f xeon_sp/{cpx,skx}: Add config IFD_CHIPSET 'lbg'
This is needed for ifdtool -p to detect CPX and SKX Lewisburg PCH as IFDv2.

Change-Id: I21df9f700aedf131a38a776e76722bf918e6af84
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55746
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 04:12:18 +00:00
Yu-Ping Wu a4a160611d soc/mediatek/mt8195: Utilize the retry macro
Make use of the retry macro intruduced in CB:55778:

 helpers: Introduce retry macro
 (Change-Id: I421e4dcab949616bd68b3a14231da744b9f74eeb)

BUG=none
TEST=emerge-cherry coreboot
BRANCH=none

Change-Id: Ieaec95e20e5bb54fcd145007cc46f21c8b7e26d2
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26 10:09:20 +00:00
Yu-Ping Wu fc3576ab06 helpers: Introduce retry macro
Introduce a macro retry(attempts, condition, expr) for retrying a
condition, which is extensively used in coreboot.

Example usage:

 if (!retry(3, read32(REG) == 0, mdelay(1))
         printk(BIOS_ERR, "Error waiting for REG to be 0\n");

BUG=none
TEST=make tests/commonlib/bsd/helpers-test
TEST=emerge-cherry coreboot
BRANCH=none

Change-Id: I421e4dcab949616bd68b3a14231da744b9f74eeb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26 10:09:06 +00:00
Nico Huber 6cd4d32039 cbfstool: Unset ${DEBUG} when making vboot hostlib
Vboot's Makefile is controlled by a ${DEBUG} environment variable.
As the name is very generic, it may be set by accident without any
intention to change the build. Having it set would break reproduci-
bility at least but it also turns out that the hostlib build would
be incomplete so that linking cbfstool fails due to internal calls
to vb2api_fail() which is not built in.

Change-Id: I2a9eb9a645c70451a320c455b8f24bfed197117c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26 10:07:34 +00:00
Ronak Kanabar d7f592deef vendorcode/intel/fsp: Remove deprecated header
FirmwareVersionInfoHob.h is removed in JSL FSP v2376 so
remove it from Jasper Lake vendorcode.

BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.

Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1

Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-26 10:06:52 +00:00
Ronak Kanabar 89316b6c6f soc/intel/jasperlake: Select DISPLAY_FSP_VERSION_INFO_2
Select DISPLAY_FSP_VERSION_INFO_2 for Jasper Lake soc.

BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.

Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1

Change-Id: If68b704c4304357b0046a510545fc213d7ed5887
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45907
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-26 10:06:40 +00:00
Arthur Heymans 5cb24d4522 soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard
It looks like the 'clear_car' code does not properly fill the required
cachelines so add code to fill cachelines explicitly.

Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26 10:06:23 +00:00
Johnny Lin e273a02d25 util/ifdtool: Add Xeon SP Lewisburg PCH platform support under IFDv2
After commit 8c082e5fe (util/ifdtool: Use -p platform name
to detect IFDv2 platform and chipset) w/o this xeon_sp/cpx would be
detected as IFDv1 and see build error.

Fixes: 8c082e5fe ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I444e7d35a85d9d42fc25d654e57386f38cf1ec85
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26 10:05:53 +00:00
Casper Chang 181fce25d9 mb/google/brya/variants/primus: init overridetree for Primus
init overridetree.cb based on the schematic ver MB_20210616C.

BUG=b:191897776, b:191897775

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I185b36e34d24b703092e3798e91c70ce3912b11f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-26 04:07:49 +00:00
Frans Hendriks 57e55148f4 mb/facebook/fbg1701/fbg1701/vboot-rw.fmd: Correct FMD statement
CB:55452 uses FMAP instead of "cbfs master header".
The flash size statement in vboot-rw.fmd does not contain the start
address, resulting in a non-booting system.

Add start address to FLASH statement.

BUG = N/A
TEST = Boot Facebook FBG1701

Change-Id: Id05ad33babb416a37c657b25cdb1e98d47c1a56d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-25 15:53:10 +00:00
Matt DeVillier 8f9ee36c53 mb/google/{octopus,reef}: Fix size of SI_BIOS region in default.fmd
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000.

This fixes build failure when selecting the option to validate the
layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR)

Test: build google/casta successfully with IFD validation selected

Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 15:52:51 +00:00
Arthur Heymans e243a60efe security/intel/cbnt: Remove fixed size requirement
The CBnT provisioning tooling in intel-sec-tools are now cbfs aware
and don't need to have a fixed size at buildtime.

Tested on OCP/Deltalake with CBnT enabled.

Change-Id: I446b5045fe65f51c5fa011895cd56dbd25b6ccc7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55821
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 15:52:05 +00:00
Martin Roth 8a85a84fac Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80s
Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in
bootblock.

BUG=b:191370340
TEST: Build with & without the option enabled

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-25 15:51:20 +00:00
Malik_Hsu b8bba6519e mb/google/brya/variants/primus: add dram part id
This change adds mem_parts_uesd.txt that contains the only
memory parts used by primus for Proto build and Makefile.inc
generated by gen_part_id.go using mem_parts_used.txt.

BUG=b:186091208,b:189169995

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25 15:03:14 +00:00
Sheng-Liang Pan 36572cade4 mb/google/volteer/var/chronicler: add chronicler memory configuration and gpio and devicetree settings
add memory configuration for chronicler,
based on schematic and gpio table, update gpio and devicetree settings for chronicler.

BUG=b:187318819
BRANCH=None
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
verify bootable with chronicler

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 06:30:44 +00:00
Angel Pons adeac8d4f7 soc/intel/apollolake: Drop `xdci_can_enable()` call
The `xdci_can_enable()` function is called earlier to configure FSP-S
UPDs. If it returned false, then the xDCI device will be disabled and
the second `xdci_can_enable()` call will never be evaluated.

Change-Id: I4bd08e3194ffccc79c8feaf8f34b2bb4077f760a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55789
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 06:28:11 +00:00
V Sowmya 6464c2aa4f soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param
This patch fixes the typo introduced in commit b03cadf for renaming
FSP_S_CONFIG param name to s_cfg.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I0a9b500e528c68033008f3f8955d6c9c9ba8a737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-25 06:26:46 +00:00
Nico Huber f22f408956 cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.

This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.

Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-25 04:28:36 +00:00
Frans Hendriks cd85aac434 mb/facebook/fbg1701/fbg1701/Kconfig: Update VBOOT key location
Error Could not add [key.vbpubk]: too big occurs, when Eltan verified boot is enabled.

Update value of VENDORCODE_ELTAN_VBOOT_KEY_LOCATION.

BUG = N/A
TEST = Boot Facebook FBG1701 with Eltan verified boot enabled.

Change-Id: I1faecd189915985df633ac74627fd872ce8867f0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25 04:25:42 +00:00
Angel Pons 50b92f9a82 soc/intel/apollolake/xdci.c: Use `dev` parameter
The `dev` parameter already points to the xDCI device.

Change-Id: I122cc642c86b30804dd1176f77f4e2e1ebea4aa0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55788
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:24:09 +00:00
Angel Pons 9bf9adae13 soc/intel/skylake: Use `devfn_disable()` to handle XDCI
Done for consistency with other Intel SoCs. This allows moving the
pattern inside a helper function.

Change-Id: If95c4b6c1602e56436150a931210692f14630694
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55787
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:22:42 +00:00
Angel Pons 7ff3f31cd1 soc/intel/skylake: Use `is_devfn_enabled()`
Use the `is_devfn_enabled()` function for the sake of brevity.

Change-Id: Ic848767799e165200f26c2d5a58fbd3b72b9c240
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55786
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:21:56 +00:00
Kevin Chiu bb0c404e6e mb/google/octopus: add audio codec into SSFC support for Garg/Garfour
BUG=b:191213716
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:20:11 +00:00
Ronak Kanabar f7e8adac7b edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h
Update MdePkg/Include/IndustryStandard/SmBios.h to avoid compilation
errors through safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2
Kconfig.

BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patches in relation chain
and verify the version output prints no junk data observed.
Couple of lines from logs are as below.

Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1

Change-Id: I9698861be1f969ddca7f171767a54ac486502c74
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45906
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:19:08 +00:00