Commit Graph

49295 Commits

Author SHA1 Message Date
Jason Glenesk 3c35a5b7ec 3rdparty/amd_blobs:Advance submodule pointer
This picks up the following changes:
  0966b9b7 Drop placeholder Sabrina binaries
  846d7032 Add Cezanne FSP binaries
  5ecc861c Update PSP binaries for Cezanne
  43136aad mendocino: Add stripped microcode patch

Change-Id: I9ff0b581e831ca7190df194c7d1f5162d2641d12
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68022
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 19:00:26 +00:00
Felix Held 3dfb485334 util/amdfwtool/data_parse: fix PMU subprogram/instance ID handling
The parsing of the PMU binary subprogram and instance numbers only
worked correctly for the cases where the ID in the name in the fw.cfg
file was between 0 and 9, but returned wrong results if it was between a
and f. Switch to using strtol with a base of 16 instead of subtracting
the char '0' from the char in the filename in
find_register_fw_filename_bios_dir to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30 18:03:50 +00:00
Himanshu Sahdev 542ac2f3f8 guybrush: mark RO_GSCVD area unused
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.

Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the
RO section up by 8K, they were misaligned. Hence marking this area as
unused instead of removing the same to work around ChromeOS
infrastructure shortcoming.

Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 17:58:47 +00:00
Lean Sheng Tan 2ddcf409c3 mb/prodrive/atlas: Add Kconfig option to enable SaGv
It turns out that one can use Kconfig options to specify values for
devicetree options, as long as the resulting expression is a compile
time constant. Use this to configure SaGv for Atlas: enable it by
default, but allow SaGv to be disabled manually for convenience when
testing. Enabling SaGv makes MRC train the RAM multiple times, which
takes a significant amount of time.

For further info on SAGV on ADL, please refer to Intel Doc 655258
(Alder Lake Datasheet) section 5.1.3.2.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 16:51:00 +00:00
Lean Sheng Tan 1ec8f97782 soc/intel/adl: Add config option to enable FSP-S SATA test mode
For further info on SATA test mode, please refer to this doc:
https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 16:50:38 +00:00
Tim Wawrzynczak 7c3e48c573 MAINTAINERS: Remove Tim W as maintainer from all but ACPI
I will no longer be working on coreboot professionally anymore, so
update the MAINTAINERS file to reflect that; I leave myself as an ACPI
maintainer as I would still like to keep working with the coreboot
community :-).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf3f93ad876071cd6c24705dd61a9c98e397fba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30 16:40:13 +00:00
Felix Held 2e785705f2 soc/amd/common/psp_verstage/fch: use [read,write]8p to avoid typecasts
Also add missing device/mmio.h include.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I03af0772c735cdc7a4e221770dc528724baa7523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67983
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:50:03 +00:00
Felix Held b7a4a430c0 soc/amd/common/block/smbus/smbus: use [read,write]8p to avoid typecasts
Also add missing device/mmio.h include.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f3f7ea36896c8e55c62acd93fe8fc4fb7c74b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67982
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:49:49 +00:00
Felix Held 51f60578bb soc/amd/common/block/spi/fch_spi_util: use [read,write][8,16,32]p
Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8573217d3db5c9d9b042bf1a015366713d508c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67981
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:49:43 +00:00
Felix Held 6f9e817bbf soc/amd/common/block/lpc/espi_util: use [read,write][8,16,32]p
Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51c6f5c73b41546b304f16994d517ed15dbb555f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:49:33 +00:00
Felix Held 25866fe893 soc/amd/cezanne,mendocino,picasso/uart: use write16p to avoid typecasts
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6e743068dfcf9d393096f775759181af1a1c470d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67979
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:49:25 +00:00
Felix Held f69cb29c20 soc/amd/picasso/fch: use [read,write]8p to avoid typecasts
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8445f209e43366b43b9c4750bc5f074f6d4144aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67978
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:49:18 +00:00
Felix Held 78ba98a797 soc/amd/stoneyridge/fch: use read[16,32]p to avoid typecasts
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6372741284ad5f0453f0d4dfd8ebaddd7385f8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67977
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 14:49:07 +00:00
Tim Van Patten 73a0d0af64 mb/google/skyrim/Kconfig: Enable DPTC and No Battery Mode
Enable DPTC and No Battery Mode for Skyrim. This allows Skyrim to boot
without a battery or with a critically low battery.

DPTC remains disabled for the Winterhold and Morthal variants until it
can be tested on those boards.

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim with low & no battery

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icc4084476916cc8e142908d8e58baf7124568b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67211
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 13:19:43 +00:00
Reka Norman d9cb72559f mb/google/nissa: Change TPM I2C freqeuncy to 1 MHz
Change the TPM I2C freqeuncy to 1 MHz for nivviks and nereid, and in
the baseboard. Other nissa devices will be changed after verification.

This saves 11 ms of boot time on nivviks and nereid.

400 kHz:
504:finished TPM initialization                       272,304 (35,730)
...
512:finished TPM PCR extend                           526,250 (23,729)
513:starting locking TPM                              526,250 (0)
514:finished locking TPM                              535,106 (8,855)
  6:end of verified boot                              543,927 (8,821)

1 MHz:
504:finished TPM initialization                       266,293 (30,747)
...
512:finished TPM PCR extend                           513,711 (20,108)
513:starting locking TPM                              513,711 (0)
514:finished locking TPM                              521,311 (7,599)
  6:end of verified boot                              528,893 (7,581)

BUG=b:249201598
TEST=On nivviks and nereid, all timing requirements in the spec are met.
Frequencies:
nivviks - 972.01 kHz
nereid  - 968.99 kHz

Change-Id: I9dd783527d4215ed7d79d69853a1f321ea2d8a28
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-30 13:19:05 +00:00
V Sowmya a88d5e3bca mb/intel/adlrvp_n: Disable the External 1.05v VR in S0
Disable the external 1.05v VR in S0 as a fix for the
display flicker issue in ADL-N.
Please refer the Doc with ID 742988 for more details.

BUG=b:248249033, b:245970842
TEST=Verified that the display flicker issue is fixed.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If9f40e6c37e80caceb726a8e5f4d4b14dc479858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67654
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-30 13:16:13 +00:00
V Sowmya 662bbcfe72 mb/google/nissa: Disable the External 1.05v VR in S0
Disable the external 1.05v VR in S0 as a fix for the
Display flicker issue in ADL-N.
Please refer the Doc with ID 742988 for more details.

BUG=b:248249033, b:245970842
TEST=Verified that the display flicker issue is fixed.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaa53bfd99a550b2cffcdaee640ee3a429e93aef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-30 13:15:59 +00:00
Matt DeVillier fcfa4addd1 mb/google/guybrush: enable display backlight in ramstage
Commit c7204b5a4 [mb/google/guybrush: Enable backlight in the OS]
disabled the GPIO for the display backlight in favor of using ACPI
to enable it, but this breaks display output for payloads which do
not/can not enable the backlight GPIO themselves (edk2, grub, SeaBIOS).

Re-enable the GPIO for display backlight so that payloads other than
depthcharge work properly.

TEST=build/boot google/dewatt with Tianocore payload, verify payload
display visible.

Change-Id: I2519d779954ed89486045aa7de0b18f1c31a4374
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-30 13:15:22 +00:00
Michał Żygowski 283e5876b5 drivers/crb: Add SMBIOS hook to generate type 43 TPM Device
Example for Alder Lake PTT:

Handle 0x004C, DMI type 43, 31 bytes
TPM Device
	Vendor ID: INTC
	Specification Version: 2.0
	Firmware Revision: 600.18
	Description: Intel iTPM
	Characteristics:
		TPM Device characteristics not supported
	OEM-specific Information: 0x00000000

TEST=Execute dmidecode and see the type 43 is populated with PTT
on MSI PRO Z690-A WIFI DDR4

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I05289f98969bd431017aff1aa77be5806d6f1838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-30 08:21:01 +00:00
Michał Żygowski e779523193 smbios: Add API to generate SMBIOS type 43 TPM Device
Based on DMTF SMBIOS Specification 3.1.0.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-30 08:20:23 +00:00
Elyes Haouas 7ac796c7b2 mb/ocp/{deltalake,tiogapass}: Replace comma with semicolon
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie564d080955097b416943e772de6c62708ce5764
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30 06:17:38 +00:00
Robert Zieba de6ecd0101 util/spd_tools: Change Mendocino to use 0x13 for LP5x memory type
Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.

BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13

Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-29 17:12:00 +00:00
Fabio Aiuto 45aae7f10f treewide: use is_enabled_cpu() on cycles over device list
use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.

TEST: compile test and qemu run successfully with coreinfo
payload

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-29 16:47:04 +00:00
Fabio Aiuto c5573d62b7 include/device/path.h: use functions for enabled cpu selection
Add function defs and prototypes of functions checking whether
a device is {a cpu,an enabled cpu}

TEST: compile test and qemu executed successfully with
coreinfo payload

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: Iabc0e59d604ae4572921518a8dad47dc3d149f81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-29 16:46:41 +00:00
Elyes Haouas 712c70b357 nb/intel/i945/raminit.c: Use read32p()
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic0361e5d928c24cfe7dc0a8b0385fbe73d906b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62365
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-29 13:41:46 +00:00
Elyes HAOUAS 3cd00dbb3e arch/x86/idt.S: Use 'iretq' for ENV_X86_64
Fix the warning below when building GA-945GCM-S2L with 64-bit:
src/arch/x86/idt.S:216: Warning: no instruction mnemonic suffix given and no register operands; using default for `iret'

Change-Id: Ibbc106714e25293951a71d84fea0a660f41f9c02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-29 13:41:06 +00:00
Subrata Banik 0d3e3f54c5 mb/google/rex: Enable EC SW Sync
This patch de-selects EC software sync config and enable early
EC Software Sync.

BUG=b:248775521
TEST=Able to perform EC sync on Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bf8018e8a3fd06bb98c82a27d12883fc8d3a5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-29 13:40:10 +00:00
Matt DeVillier cfec5ddc16 mb/google/skyrim: Rename pcie_gpio_table to romstage_gpio_table
Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs.

Rename the getter function to match.

Change-Id: I285602209072247895c2cb0830f3faf675328757
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-28 21:29:59 +00:00
Matt DeVillier 4236e2a23a mb/google/skyrim: rename baseboard GPIO table getter for clarity
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

Change-Id: Icebf7e11736929389227063039575a4c5ecf3840
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-28 21:28:59 +00:00
Denis 'GNUtoo' Carikli b82486496d intelmetool: Add PCI ID for Bay Trail
Tested on a Dell Venue 8 Pro tablet

Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-28 18:22:27 +00:00
Sergii Dmytruk 68eef53ead payloads/external/skiboot/Makefile: fix output on `make clean`
skiboot's Makefile always executes $(CC) to determine whether its clang
or GCC and not setting CROSS for clean target results in this annoying
output (assuming `powerpc64-linux-gcc` isn't available):

    make[2]: powerpc64-linux-gcc: No such file or directory

Change-Id: I242b2d7c1bdf1bbd70fd4e4e0605341fe8301ca5
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-09-28 17:35:37 +00:00
Daniel Kang 84656e15c9 mb/google/rex: Set up MIPI cameras via ACPI
This patch adds ACPI configurations of 8MP YHUX and 2MP CJFKF28-1
as world- and user-facing cameras of Rex.

BUG=b:246413264
TEST=Verified world- and user-facing cameras using Chrome Camera App on
Google/rex device.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Iaaa16e491a66500606b3a9eb1d87f396641778e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-28 16:13:26 +00:00
Elyes Haouas bdef1cdebd include/reg_script.h: Remove trailing semicolon
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib2c1738b7b6a6db1fa57ea34fb50588388140a51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-28 16:12:24 +00:00
Elyes Haouas 5899b0d2b9 include/memrange.h: Remove trailing semicolon
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia0c4fd6d20c92caea379ef02e020ab9294ed0ffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-28 16:12:04 +00:00
Shon Wang e30695dbe1 mb/google/brya/vell: Add PS1/PS2 cutoff point
According intel Doc#634254 and Doc#608715
PS2/PS1 cross point = 5
PS1/PS0 cross point = 10
PS2 cutoff = 1.4*(PS2/PS1 cross point) = 7

1.3 is better magnification, it obtain by test
PS1 cutoff = 1.3*(PS1/PS0 cross point) = 13

BUG=b:241850120
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'

Change-Id: I83e9682004e2c3644ad4a5565e6ab85be48ba22f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-28 15:10:00 +00:00
Ian Feng 738a385b66 mb/google/nissa/var/xivu: Disable CNVi WLAN/BT
Xivu uses PCIE WLAN, so disable the CNVi WLAN/BT.

BUG=b:247120749
TEST=Boot to OS on xivu and check that WLAN/BT still works.

Change-Id: I968d383278bd50268d899cff82067ceb7c3ba5ed
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
2022-09-28 15:09:46 +00:00
Matt DeVillier 52a22fa7e6 mb/google/octopus: rename baseboard GPIO table getter for clarity
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

Change-Id: I17db734784ce96cdf5e0486dc2ad057d73bfb15f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-28 15:09:29 +00:00
Matt DeVillier bbf2706fb4 mb/google/octopus/ampton: Use variant_override_gpio_table
Rather than duplicating the entire set of GPIOs from the baseboard, use
the variant_override_gpio_table() method like all other octopus
variants do.

TEST=build/boot ampton, dump GPIOs and verify unchanged.

Change-Id: I36aa25bbee7c21a51d9fdd40405f492082455d9c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-28 15:09:15 +00:00
Venkat Thogaru 209efccba6 sc7180: Update correct path of reset.h header file
Updated reset.h header file path and sorted alphabetically

BUG=b:236990316
TEST=Validated on qualcomm sc7180 development board.

Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: Ibf92df160a6f8ba588310508812a5601e68a887e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-09-27 23:13:27 +00:00
Nick Vaccaro 9bf8f6bd90 mb/google/brya/variant/brya0: Add two new memory parts
Add support for the following two new memory parts to support a new
SKU that has two memory options that brya0 does not have:
  MT53E2G32D4NQ-046 WT:C
  MT53E512M32D1NP-046 WT:B

BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash a skolas with
an image-brya0.serial.bin and verify it boots successfully to kernel.

Change-Id: I28667918e5a183339febdc054465effeac8bddbe
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67879
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-27 21:52:41 +00:00
Angel Pons c6df44b959 ec/lenovo/h8: Add Kconfig option for Fn-Ctrl swap
Having to use a runtime configurable option backend like CMOS just to
specify the value of the "fn_ctrl_swap" option is annoying. Introduce
a new Kconfig option to allow specifying the fallback value, which is
only used when the option backend cannot provide a value.

Change-Id: I00bb3cd60c443fc0c8adb82e8e0c436dfc5de24b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67836
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-27 16:19:09 +00:00
Matt DeVillier acc91c335b mb/google/dedede: rename baseboard GPIO table getter for clarity
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

Change-Id: I11814016d654bc2c2e6d24b3d18fb30d5b843fe9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-27 15:16:49 +00:00
Matt DeVillier 6b8728f3ad mb/google/volteer: rename baseboard GPIO table getter for clarity
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

Change-Id: Id1e1a67608454466dc65bf4c4985cf4eba84c97d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-27 15:16:15 +00:00
Matt DeVillier 2f4b31f5a0 mb/google/guybrush: rename baseboard GPIO table getter for clarity
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

Change-Id: Ib8439e664defeafd2d08cffb74c997ab69230231
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-27 15:15:51 +00:00
Matt DeVillier 4a16be91dd mb/google/zork: rename baseboard GPIO table getter for clarity
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

Change-Id: Iaa3c9404919fd6c43596d7b27cfab43a1a5b0b21
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-27 15:15:39 +00:00
Fabio Aiuto fdcf698a89 acpi/acpi_pm.c: refactor acpi_pm_state_for_* functions
Use just one function to get the chipset powerstate and add an argument
to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the
failure log accordingly.

TEST: compile tested and qemu emulation successfully run

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-27 14:19:01 +00:00
V Sowmya e6d6d3620e drivers/intel/mipi_camera: Remove IPU ES support entry for ADL-N
The current IPU ES entry value is always set to true for ADL-N and
kernel picks the ES version of the main IPU FW even for the production
bootloader but loading is not successful due to the authentication
failure.

Alderlake-N silicon has the same CPU id for all the SKU's and
also the production binaries are backward compatible with ES parts.
This change removes the IPU ES support ACPI entry since the
kernel needs to load the production IPU main firmware on both the
ES/QS parts.

BUG=b:248249032
TEST=Verify the Camera functionality by enabling the IPU secure mode
on ADL-N variants with both ES/QS silicon.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I75b222e6f2b1ccdc5b6c448eb60afff3c1da3a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-09-27 14:18:27 +00:00
zhaojohn ff69f5cb3f mb/google/rex: Allocate resources for PCIe TBT root port
This patch selects the SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to allocate
TBT/USB4 root port resources for PCIe tunneling.

BUG=b:248328015
TEST=Built image and verified TBT/USB4 tunneling functions on Rex.

Change-Id: I69f4d26bb7b3d74dbda068add284a69f1bbeff40
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-26 14:23:09 +00:00
Matt DeVillier 0208b51215 Documentation/drivers: Add section for i2c detect feature
Add a section explaining how the detect feature works and when it should
be used.

Change-Id: Ife5178d4565e76d0ff436c835c9c47525015c3ed
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-26 14:21:54 +00:00
Tim Wawrzynczak 72bae5b9bd mb/google/brya/var/agah: Explicitly program GPP_H13 in ramstage
In order that GPP_H13 not use the GPIO override programming from its
baseboard (brya), explicitly program GPP_H13 to a output HIGH instead
of relying on the 20K pullup from the baseboard.

BUG=b:240617195
TEST=SSD still functional

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iddedebe2d5cfc0123932b14980d1268bcb147703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-26 14:21:37 +00:00