We need to support RTC in ramstage so that we can see correct timestamp
in ChromiumOS eventlog.
BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui
Change-Id: Idb0fe5c05e4ecdf0e6398e3c781c71d14f85f19b
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The values from auxadc may be incorrect if not calibrated by efuse.
Without calibration, the value error range is about +/-50mv,
and after being calibrated the error range is about +/-10mv.
BUG=b:131391176
TEST=make clean && make test-abuild; boots on Kukui rev 2 units.
BRANCH=none
Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: JG Poxu <jg_poxu@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust FMAP sections that
- ELOG only needs 4K (by driver limitation)
- SHARED_DATA only needs 4K or less (for netboot params)
- SMMSTORE is probably not needed since UEFI@ARM is not available yet
- VPD can be smaller (most x86 devices have only 16/8K for RO/RW)
- Increase RW_LEGACY to 1M (recommended value)
- Move all new saved space to CBFS
BUG=b:134624821
TEST=Built Kukui image and boots on Rev2 units.
Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
'else' is not needed after a 'break' or 'return'.
Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Free the tree before returning to prevent a leak.
Change-Id: I1132c0e7404eec1af3adc19a83257f28563f8a58
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Coverity believes there is a path where StdHeader is possibly
null. This *should* be incorrect, since the header is actually
initialized through the module dispatch framework, though Coverity
can't see it due to the extensive type-punning. However, the control
flow is so dizzingly complicated that I'm not even completely sure,
so adding an extra assert to be careful won't hurt anyway.
Change-Id: If3d7c5d5c5bba846e7453b3dbc824e2208d749fb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1379932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The case when Speed == 5 is already dealt with on line 111.
Change-Id: Icc41c00fb333a51001568f588c17f7b6c6a3a923
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229626
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This check is already performed at the beginning of
dct_ddr_voltage_index().
Change-Id: Ia73025333c152f14249afb16d05f66791e69e7cb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347322, 1347323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This conditional is exactly the same as the one right below it, except
the operations are reorganized slightly.
Change-Id: I00c19a467d23a0736bc2a33b516f97080039e634
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Logging and clearing the recovery mode switch doesn't have
anything to do with vboot_handoff. Move it to the main verstage
logic file.
BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2e74f3893463e43fe5fad4a8df8036560f34e0db
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These functions are no longer used and may be removed:
* vboot_handoff_check_recovery_flag
* vboot_get_handoff_flag
BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ie05652ef1288eef74bd2e7e8bea79fd29d523859
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Two functions retrieve vboot recovery_reason:
* vboot_handoff_get_recovery_reason
* vboot_get_recovery_reason_shared_data
Previously, when CBMEM comes online, a vboot_handoff data
structure is created, and depending on the architecture,
coreboot may eventually lose access to vboot_working_data.
After implementing vboot_working_data CBMEM migration,
vboot_working_data is always guaranteed to be accessible.
vboot_get_recovery_reason_shared_data is corrected to also
allow accessing vboot_working_data in ramstage and postcar.
Now, vboot_handoff_get_recovery reason returning a valid recovery
reason implies that vboot_get_recovery_reason_shared_data should
*also* return a valid recovery reason. Thus we may remove the
former.
BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Iac216dc968dd155d9d4f8bd0f2dfd5034762f9a0
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.
BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter
Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Intel Braswell supports i2c block writes using SMBus controller.
This support is missing in actual smbus routines.
Add do_i2c_block_write() which is a based on do_smbus_block_write() but
also write first byte to SMBHSTDAT1.
The caller needs to configure the SMBus controller in i2c mode.
In i2c mode SMBus controller will send the next sequence:
SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT
To ensure the the command is send over the bus the SMBHSTCMD register must
be written also
BUG=N/A
TEST=Config eDP for LCD display on Facebook FBG-1701
Change-Id: I40f8c0f5257a62398189f36892b8159052481693
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb
Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.
BUG=none
TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LONG_FADT is not used at all. So remove it and use sizeof(acpi_fadt_t) for
header length.
Change-Id: I433d1b2e0f3b9505d7c52eb14f1a476fbe52a284
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553
BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.
Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.
Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).
BUG=b:126593573
TEST=Used with WIP Picasso
Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit follows up on commit commit 89989cf6 with Change-Id:
I1f44ffeb54955ed660162a791c6281f292b1116a ("src: Drop unused include
<arch/acpi.h>").
Change-Id: I3dc12373b32b95d25ba7b302cbca5f927678315d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33365
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit follows up on commit 8b7a1614 with Change-Id:
I73c557d6ef009fb2cac35fdea500dee76f525330 ("src/mainboard: Remove
unneeded include <arch/io.h>").
Change-Id: I7f307bf5b6cdcfebe1a290ce344b962fcecc8781
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were
already pushed in https://review.coreboot.org/c/coreboot/+/33031
Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
As CFLAGS_GCC and CFLAGS_CLANG are still the same at this point, this
just removes some duplicate flags.
Change-Id: I532e5fa146891b70e4c1949c614b280055524593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Print I2C SAR device info so that it is available in cbmem logs.
BUG=none
BRANCH=none
TEST=Boot up and check cbmem -c can find the SAR I2C info
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia143932bb660ed2c2cea76310f11ede2b727adf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33432
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
data &= !BIT0 will clear data, since !BIT0 evaluates to 0 (oops). We
only want to clear bit 0, not the whole thing, so use bitwise negation
instead.
Change-Id: I2179119e0d2d4aceaf4f8b499bf4c5baf4ef677f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1241812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This was done to update the global variable g_ichspi_lock but this is
now removed in favor of reading the lock bit during runtime instead of
keeping track of the state.
Change-Id: I8cb69a152b0e050d64d8979ee92de2d24136f8dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33390
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI swseq controller can be locked in other parts of the code, for
instance when it's locked down in the finalize section. The driver
has to be made aware of that. The simpler solution is to not keep
track of the state and simply read out the lock bit on each SPI
transfer.
Change-Id: Ifcd5121b89d6f80fc1c1368786982d0d9fa1bf61
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We had a value that was overloaded thrice.
By moving them in a common structure and ordering them by value such
issues are hopefully avoided in the future.
Also add a few values to libpayload that were only defined in
commonlib.
Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32958
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We had a value that was overloaded thrice.
By moving them in a common structure and ordering them by value such
issues are hopefully avoided in the future.
Change-Id: I0c7762601d7620413989b458fa634d7606accc9d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32957
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add maintainers to the new vendorcode.
Change-Id: Ie3f99dd99c708f93bfcd19f52c57504e157e1eca
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
You-Cheng Syu