* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Set the payload argument in selfload, as other (non self) payloads, are
going to set a different argument.
Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression (supposedly) after commit:
23d62dd lib/bootmem: Add more bootmem tags
Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite
memory regions of the running ramstage. This case is handled
gracefully via a bounce-buffer implementation in arch/x86/boot.c.
Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Making exceptions for some payload to be loaded near
and under 1 MiB boundary sounds like a legacy 16-bit
x86 BIOS thing we generally do not want under lib/.
Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With RELOCATABLE_RAMSTAGE, variables RAMBASE and RAMTOP
have no meaning any more.
Change-Id: I711fe98a399177c2d3cb2a9dcdefba61031fb76d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the last bits of building romstage with romcc.
Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Symbol defined in via/cx700 but also used elsewhere.
Change-Id: I31d6043e71dea474de00f609b9609a628ecc6eb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
The recursive method calling this function has been changed to
handle a null return from acpi_device_name and abort instead of
continuing and perhaps forming an invalid ACPI path.
Change-Id: Ic17c5b6facdcb1a0ac696912867d62652b2bf18e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 8ccf59a947.
This wasn't meant to be submitted yet and seems to be causing issues,
just as Patrick warned me..
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I8c4b57ba92ef4e0535e4975485188114a1084f09
Reviewed-on: https://review.coreboot.org/26452
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the recent change 4c518e1 (timestamp: Add timestamps for TPM
communication) to add more timestamps for TPM communication, now we
are overflowing the TIMESTAMP region in verstage. This change
increases TIMESTAMP region size to 512 bytes to accomodate this.
BUG=b:79888151, b:79974682
Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In case the Option ROM isn't a multiple of 4KiB the last buffer was
truncated to prevent a buffer overrun. But tests on nouveau showed
that nouveau expects a buffer that has the requested size and is zero
padded instead.
Always return a buffer with requested size and zero pad the remaining
bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple
of 4 KiB.
Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This reverts commit 717ba74836.
This breaks seabios and a few other payloads. This is not
ready for use.
Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, adding a payload to CBFS using the build system, the warning
below is shown.
W: Unknown type 'payload' ignored
Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.
Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for writing ACPI _PLD structures that
describe the physical location of a device to the OS.
This can be used by any device with a physical connector, but is
required when defining USB ports for the OS.
A simple function is provided that generates a generic _PLD
structure for USB ports based on the USB port type.
Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit adds support for writing ACPI _UPC structures that
help describe USB ports for the OS.
This is a simple structure format which indicates what type of
port it is and whether it is connectable. It should be paired
with an ACPI _PLD structure to define USB ports for the OS.
Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds new macros to define gpio with an option to either
enable irq wake (mark it as ExclusiveAndWake flag in SSDT) or disable
it (mark it as just Exclusive flag in SSDT).
Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/25838
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MMConf is not architecture specific. We also always provide a
pci_bus_default_ops() now if MMCONF_SUPPORT is selected.
Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26062
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I54bebc245df6e967acd30a0b029557e23f8da529
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:
BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
should not be touched by bootmem (by example: stack,
TTB, program, ...).
BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should
not be touched by bootmem.
Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.
Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.
ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.
ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.
Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In each stage keep GDT in the code region. This accommodates
platforms, such as glk, that are executing out of CAR. The
gdt is small and loading it is trivial so just do it unconditionally
instead of introducing another Kconfig.
BUG=b:78656686
Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Now that VBOOT_STARTS_IN_BOOTBLOCK depends on C_ENVIRONMENT_BOOTBLOCK,
remove the complications in assembly_entry.S. There's no platform
utilizing romcc bootblock and needing to handle verified boot after
bootblock as well as not using verified boot. That combination makes
things very complicated. Clean up the complication as it's not a
combination that needs to be supported.
BUG=b:78656686
Change-Id: Ie2960790d60ccb8d5b75dab507fe70a6563b3d34
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25968
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some touchscreens need to adhere to certain timings during the power
off sequence as well as during the power on sequence. Adding
reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to
accommodate these devices.
BUG=b:78311818
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.
Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.
Tested with uImage payload on Cavium SoC.
Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
New API required by sdm845 DDR init/training protocol
TEST=build & run
Change-Id: I8442442c0588dd6fb5e461b399e48a761f7bbf29
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Linux (4.16) assumes that the PIT interrupt is connected to the pin 0 of the
IOAPIC[0] and panics otherwise.
This might be a Linux bug. The MP Specification 1.4 does seem to mandate
sequential ordering for bus entries, but not for the I/O APICs.
Change-Id: Ibf823eb5b3a29e4590cba915069cdfe5f780edcd
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RISC-V doesn't set up page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").
Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that assembly code isn't processing the idt gates there's
no need to ensure each vector entry is the same amount of code.
BUG=b:72728953
Change-Id: I2b248b26b9df36d6543163762c74622f79278961
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having
the interrupt handling code available to all stages. In order
to do this the idt setup is moved to a C module. The vecX
entries are made global so that a table of references to all
the interrupt vector entry points can be used to dynamically
initialize the idt. The ramification for ramstage is that
exceptions are initialized later (lib/hardwaremain.c). Not
all stages initialize exceptions when this Kconfig variable
is selected, but bootblock for the C, stages using
assembly_entry.S, and of course ramstage do. Anything left
out just needs a call to exception_init() at the right
location.
BUG=b:72728953
Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
CSRs are XLEN bits wide (i.e. the same width as general purpose
registers), so size_t seems a little more correct than int.
This change doesn't affect functionality because MSTATUS_MPRV already
fits in 31 bits.
Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Processors, such as glk, need to have paging enabled while
in cache-as-ram mode because the front end is agressive about
fetching lines into the L1I cache. If the line is dirty and in
the L1D then it writes it back to "memory". However, in this case
there is no backing store so the cache-as-ram data that was written
back transforms to all 0xff's when read back in causing corruption.
In order to mitigate the failure add x86 architecture support for
enabling paging while in cache-as-ram mode. A Kconfig variable,
NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
out for page tables within the cache-as-ram region. Additionally,
the page directory pointer table is also carved out of cache-as-ram.
Both areas are allocated from the persist-across-stages region
of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
the page tables.
The two paging-related areas are loaded by calling
paging_enable_for_car() with the names of cbfs files to load the
initial paging structures from.
BUG=b:72728953
Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram
is employed for that particular stage.
BUG=b:72728953
Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Patrick Rudolph