Commit Graph

47524 Commits

Author SHA1 Message Date
Werner Zeh 458cfaea9f soc/intel/apollolake: Provide FIT pointer in bootblock at build time
Before TXE releases the CPU out of reset a pointer to the constructed
FIT in SRAM is patched into the loaded bootblock at offset 4G - 64B.
Since this patched bootblock gets measured during runtime it will not
match the one that is potentially measured from the coreboot image.

This patch adds a dedicated fit.c file for Apollo Lake where the FIT
pointer is already set to the address TXE will be using at runtime.

Test=Compare sha256 sum from coreboot runtime and coreboot.rom of the
bootblock and make sure they match.

Change-Id: Ia0fd2a19517c70f50ef37e6a2dc2408bae28df10
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24 13:47:56 +00:00
Werner Zeh 859305d457 soc/intel/apollolake: Measure bootblock from IFWI
On Apollo Lake the bootblock is stitched into the IBBL IFWI region at
build time. At execution time TXE loads this IBBL into a shared SRAM
(which is read-only in this phase) and maps it at 4 GiB - 32 KiB. Then
the CPU starts to operate from this shared SRAM as it were flash space.

In order to provide a reliable CRTM init, the real executed bootblock
code needs to be measured into TPM if VBOOT is selected. This patch adds
the needed code to do this.

Change-Id: Ifb3f798de638a85029ebfe0d1b65770029297db3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24 13:45:15 +00:00
Werner Zeh 5c808e03e2 security/tpm/crtm: Add a function to measure the bootblock on SoC level
On platforms where the bootblock is not included in CBFS anymore
(because it is part of another firmware section (IFWI or a different
CBFS), the CRTM measurement fails.

This patch adds a new function to provide a way at SoC level to measure
the bootblock. Following patches will add functionality to retrieve the
bootblock from the SoC related location and measure it from there.
In this way the really executed code will be measured.

Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24 13:44:28 +00:00
Raihow Shi ca29a191d5 mb/google/brask/variants/moli: Remove stop pin declaration for LAN
Remove the stop pin declaration for LAN. Confirmed with LAN vendor,
8111K do not need to implement stop pin. It caused S0ix fail.

BUG=b:231400227
TEST=Build and suspend_stress_test -c 5 pass

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iae33068c4622f91d5cebb867e4b10f3834ce8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24 13:09:31 +00:00
Raihow Shi 604060c586 mb/google/brask/variants/moli: add fw_config for usb retimer
add USBC0_RETIMER into 2, 3 bits for usb retimer.

BUG=b:232486478
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idaf2e53387476d344d2c838a6e762f5a4c582989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24 13:08:49 +00:00
Kyösti Mälkki 68e6dc9832 device: Add log_resource()
This will replace LOG_{MEM/IO}_RESOURCE macros once
the new resource constructors are available.

Change-Id: I21b030dc42dcb8e462b29f49499be5fd31ea38f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24 13:08:00 +00:00
Werner Zeh 0c78f4c05a soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region
Add the boot flash MMIO window to the resources to report this region as
reserved to the OS. This is done to stay consistent with the reserved
memory ranges by coreboot and make the OS aware of them.
As x86 systems preserves the upper 16 MiB below 4G for BIOS flash
decoding use the complete window for reporting independent of the
actually used SPI flash size. This will block the preserved MMIO window.

Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24 13:07:34 +00:00
Dtrain Hsu 79df32d083 mb/google/brya/var/kinox: Update the DPTF parameters
Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1
values.

1. Modify baseline PL1 min_power from 15000 to 12000.
2. Modify baseline PL1 max_power from 17000 to 25000.

BUG=b:231380286
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24 13:06:55 +00:00
Vidya Gopalakrishnan 236ad4c5c6 mb/google/brya/variants/nivviks: Add DPTF passive and critical policies for Nivviks
Add DPTF passive and critical policies for ADL-N Nivviks design.
Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1.

BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board.
Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.

Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24 13:06:35 +00:00
Vidya Gopalakrishnan 9ffc9ebf25 mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variants
BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board

Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-24 13:05:57 +00:00
Lean Sheng Tan 79fe6a9537 mb/intel/ehlcrb: Adjust TSN GBE settings in devicetree
Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN
ports.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-24 13:05:21 +00:00
Werner Zeh 823b7b38e8 security/tpm/crtm: Use bootblock from FMAP on non x86 platforms
All non x86 platforms use bootblock in FMAP (see Makefile.inc). Add a
build time check for that so that all the other possibilities (CBFS or
other places for the bootblock) are dropped at build time.

Change-Id: Ic18336a0b79b5d319c2cdfecb7e1eeb89d241206
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24 13:04:25 +00:00
Arthur Heymans 9642e97c19 security/tpm/crtm.c: Fix !CONFIG_BOOTBLOCK_IN_CBFS measuring
On some platforms the bootblock is not placed in cbfs, but embedded
inside another binary that loads in into DRAM/SRAM.
e8217b11f1 (Kconfig: Add an option to skip adding a cbfs bootblock on
x86) removed adding a cbfs file containing the bootblock in that case.

Change-Id: Id47ecedbc8713ebd5d9814f1c4faf43c52780447
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24 13:03:22 +00:00
David Wu b844e6d434 mb/google/brya: Create kuldax variant
Create the kuldax variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:233380254
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULDAX

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24 12:59:36 +00:00
Ren Kuo 26bba6f29b mb/google/brya/var/volmar: Add wifi sar table
1. Add wifi sar table for volmar
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

BUG=b:233319626
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I09069bbc3a41b66ec9a88cfede46acc067209b01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-05-24 12:59:18 +00:00
Felix Singer 540473a491 3rdparty/fsp: Update submodule pointer to newest master
Updating from:
f4bbf5a Apollo Lake MR10 FSP

Updating to:
c607bab Whitley&CedarIsland: Fix link issue with newer toolchains

This brings in 10 new commits:

  * c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
  * 08c041d Alder Lake - P IoT FSP PV
  * a3dc6c6 Alder Lake - P IoT FSP PV
  * 2cedeba Alder Lake - S IoT FSP MR1
  * 72266f6 Elkhart Lake MR3 FSP
  * 48d4c23 Tiger Lake - IoT FSP 4391_03
  * e86327d Alder Lake - S IoT FSP PV
  * 478a80a Whitley FSP 2.2.0.3A
  * cb94d31 Whitley FSP 2.2.0.3A
  * d678813 Alder Lake - S IoT FSP PV

Change-Id: I2473bfa5718676e5b6c90b76a3b817cd9f55da4b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24 12:59:05 +00:00
Bill XIE 3dda4dad1d payloads/external: Add more option related to SeaBIOS and GRUB2
Also known as "SeaGRUB", running GRUB2 atop SeaBIOS proves to be a
useful configuration, since SeaBIOS has improved its hardware
compatibility. For example, some USB drive can work under SeaBIOS but
do not work under native GRUB2, and GRUB2 can use BIOS call (provided
by SeaBIOS) as a fallback method to access hardware if it is present.

But more option is added addition to "SeaGRUB": now GRUB2 and SeaBIOS
can be built as secondary payloads, and "SeaGRUB" is now implemented
as "Primary SeaBIOS + Secondary GRUB2 (selected) + config files".

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie681fa231abfe4a8f1e4510b3c17957550a9d2f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-24 12:58:52 +00:00
Elyes Haouas 26e0b94614 util/lint/checkpatch.pl: Reduce difference with linux v5.18
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24 12:57:48 +00:00
Yidi Lin f044264886 mainboard/google/corsola: Fix incorrect timestamps in the eventlog
Timestamp '2000-00-00 00:00:00' is considered as the invalid format.
Enable RTC to fix incorrect timestamp format in the eventlog.

BUG=b:232035991
TEST=check the timestamp field in /var/log/eventlog.txt

Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-05-24 07:46:26 +00:00
Subrata Banik f8d4b50a67 soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macro
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Alder Lake SoC PCI device list.

BUG=none
TEST=Able to build and boot taeko, google board.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-24 05:09:25 +00:00
Werner Zeh b60e69bde8 soc/intel/apollolake: Enable SSDT for fast SPI controller
Since the fast SPI controller is hidden on Apollo Lake the OS cannot
probe it and is therefore unaware of the reserved resources assigned in
coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to
report the reserved resources to the OS.

Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-23 14:49:10 +00:00
Arthur Heymans ea2c1d357c cpu/x86/smm: Remove heap
Currently no smihandler uses heap.

coreboot's heap manager also is quite limited in what it will
free (only the latest alloc). This makes it a bad idea to use it inside
the smihandler, as depending on the alloc usage the heap might actually
be full at some point, breaking the smihandler.

This also reduces the ramstage by 448 bytes on google/vilboz.

Change-Id: I70cd822be17c1efe13c94a9dbd2e1038808b9c56
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-23 13:53:26 +00:00
Uwe Poeche bf378a0fdf mb/siemens/mc_ehl: Disable RAPL
Disable RAPL for all mainboards based on mc_ehl for stable real time
mode of CPUs.

Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR
register are cleared.

Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-23 11:54:58 +00:00
Uwe Poeche 0ce586b1a4 soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.

On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.

Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.

Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-23 07:17:21 +00:00
Jon Murphy ac040552fc mb/google/guybrush: Remove TODO for ESPI functions
The feature request was moved to Skyrim in the interest of time
and effort.  The bug was updated to reflect this, and the comment
should be removed from the monkey island code base

BUG=b:232952508
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22 18:28:00 +00:00
Jon Murphy c44249d52c mb/google/guybrush: Remove unused sleep GPIO table
On Guybrush, there wasn't a need for a sleep GPIO table.
Remove the TODO and filler table and function to reduce
unnecessary function calls/overhead.

BUG=b:232952508
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22 18:27:26 +00:00
Felix Held 6e43836ef3 mb/gogle/skyrim/devicetree: enable display HDA device
The HD audio controller of the GPU on bus A device 0 function 1 wasn't
enabled, so it didn't get resources assigned. Enable it to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21 18:53:12 +00:00
Felix Held e0ea930296 mb/gogle/skyrim/devicetree: enable audio coprocessor device
The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't
get resources assigned. Enable the ACP device to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21 18:52:52 +00:00
Felix Held b29f7d3f8d mb/gogle/skyrim/devicetree: enable crypto device
The crypro device on bus A device 0 function 2 wasn't enabled, so it
didn't get resources assigned resulting in this the Linux kernel error:

[   38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device]
[   38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002)
[   38.582175] ccp 0000:04:00.2: ioremap failed
[   38.582178] ccp 0000:04:00.2: initialization failed
[   38.582181] ccp: probe of 0000:04:00.2 failed with error -12

Enable the crypto device to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21 18:52:35 +00:00
Mario Scheithauer 5b3ccc253f mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge
There are three external Marvell PHY 88E1512 on this mainboard. The PHY
IRQ comes with a falling edge but the EHL MAC side needs a rising edge
signal. For that reason, we need an inversion of the IRQ polarity.

Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21 17:41:16 +00:00
Mario Scheithauer dccdaceb49 soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.

Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21 17:40:52 +00:00
Eric Lai 8698a6f5a9 mb/google/nissa: Change pen garage wake to EV_ACT_ANY
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed or inserted.

BUG=b:233159811
TEST=EC wake event work as expected.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-21 17:40:23 +00:00
Sean Rhodes de198bb707 soc/intel/apollolake: Hook up Sata Hot Plug to device tree
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37d31598e87e5b625ded3186980e3aba7dcf6440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-21 16:30:08 +00:00
Sean Rhodes 2683108188 soc/intel/apollolake: Hook up Legacy 8254 Timer
Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that
isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-21 16:29:38 +00:00
Tyler Wang 59f3eb9a07 mb/google/brya/var/craask: Generate SPD ID for supported memory part
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.

H9JCNNNBK3MLYR-N6E

BUG=b:229938024
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibb111cddc00a0d066ef9792d974a6e4ad263cc99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-21 16:29:00 +00:00
Sean Rhodes f304d5ff8c mb/starlabs/lite/glk: Correct indendation in devicetree
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-21 16:26:13 +00:00
Werner Zeh 53553e8ee5 src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver
If the SPI controller is hidden from the OS (which is default on Apollo
Lake) then OS has no chance to probe the device and therefore can not be
aware of the resources this PCI device occupies. If the OS needs to move
some resources for a reason it can happen that the new allocated window
will be shadowed by the hidden PCI device resource and hence causing a
conflict. As a result this MMIO window will be inaccessible from the OS
which will cause issues in applications. For instance on Apollo Lake
this causes flashrom to stop working.

This patch adds a SSDT extension for the PCI device if it is hidden from
the OS and reports the occupied resource via ACPI to the OS. For the
cases where the device is hidden later at coreboot runtime and therefore
is not marked as hidden in the PCI device itself a Kconfig switch called
'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be
set from SOC code to override it.

Since there is no defined ACPI ID for the fast SPI controller available
now, the generic one (PNP0C02) is used.

Test: Boot mc_apl4 and make sure flashrom works again.

Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-21 16:20:17 +00:00
Tyler Wang 3c88dc85f6 mb/google/nissa/var/craask: Disable pen garage and WFC based on fw_config
BUG=b:229938024
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5770f02a6d524417be6723f7f70aa80d9452f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-21 16:18:57 +00:00
Tyler Wang 10fb9c7f36 mb/google/nissa/var/craask: Switch LTE-related GPIOs settings based on fw_config
If the LTE USB DB is connected, enable LTE-related settings.
Otherwise, disable LTE-related settings.

BUG=b:229938024, b:229048361, b:229040345
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I37719cee48370a04534067aa64a3aa77e453948a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-21 16:16:53 +00:00
Terry Chen 03bdf47102 mb/google/brya/var/crota: Enable SaGv
Enable SaGv support for crota

BUG=b:229600878
TEST=FW_NAME=crota emerge-brya coreboot

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ibc06ef19e9fbbc91ef650a4ac060ce2b7c5c25d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-20 20:27:59 +00:00
Teddy Shih 13b27a376e mb/google/dedede/beadrix: Update FW_CONFIG probe for daughter board LTE
To make sure daughter board LTE existing, we update probe to DB ports
value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11)
as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14)

BRANCH=dedede
BUG=b:226910787
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I9ab4412b614ec665fbafc998756b805591982b65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20 20:27:35 +00:00
V Sowmya fe97ad37fc mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for Nereid
This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20 20:26:58 +00:00
V Sowmya 1e44a5b0c7 mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for Nivviks
This patch configures external V1p05/Vnn/VnnSx rails for Nivviks
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20 20:26:36 +00:00
V Sowmya bccad8d0a8 mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx rails
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20 20:26:13 +00:00
Casper Chang 55c1e7f858 mb/google/brya: Disable PCH USB2 phy power gating for primus
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.

BUG=b:221461379
TEST=Verify the build for primus board

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20 16:43:03 +00:00
Tim Wawrzynczak f5cd9a15ba mb/google/brya/acpi: Add support for NBCI _DSM subfunction
The Nvidia GPU supports another function named NBCI (NoteBook Common
Interface), which has some subfunctions which are required for the
Nvidia kernel driver to consume. The specification for this function
comes from the Nvidia GN20 Software Design Guide.

BUG=b:214581763
TEST=build

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20 14:59:31 +00:00
Tim Wawrzynczak 2a9b7d9313 mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASL
The agah variant will include an Nvidia GN20 series GPU, therefore
select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective
ASL code into the DSDT.

BUG=b:214581763
TEST=build patch train

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20 14:59:03 +00:00
Tim Wawrzynczak c852533379 mb/google/brya: Add PEG and initial Nvidia dGPU ASL support
Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:

1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method

There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.

BUG=b:214581763
TEST=build patch train

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-20 14:58:46 +00:00
Arthur Heymans 2efd8315f2 lib/Makefile.inc: Add cbfs header pointer on !BOOTBLOCK_IN_CBFS
On some x86 targets it the bootblock is loaded via a different
mechanism, like via the AMD PSP or Intel IFWI. Some payloads need that
pointer so add it to cbfs.

Note that on Intel APL this file is not used, which is why the
bootblock still needs to contain the pointer in the ARCH_X86 part.
It is not worth it to add logic to specifically deal with APL as this is
a legacy feature anyway.

For AMD non-car platform this fixes cbfs access in SeaBIOS.

Change-Id: If46e80e3eed5cc3f59964ac58e507f927fc563c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-20 11:22:32 +00:00
Mario Scheithauer 5b757b597a soc/intel/ehl: Use defines for Ethernet controller IDs
Use defines for a better reading of the code.

Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-20 11:22:03 +00:00