This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Porting the feature from commit 2bc54e7c00
("soc/intel/alderlake: Add support to skip the MBP HOB")
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch drops `ufs.asl` from the local SoC directory.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
This patch includes UFS ASL entry from common block ACPI code.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia77ea1c915d0dec991afa5b977af78487ae6a8b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68301
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
This patch migrates UFS ASL entry from Alder Lake SoC to common
block ACPI code to be able to be utilized across different IA SoCs.
Additionally, migrate to ASL2.0.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2e803138a20fd1fc3cdcd5c0fbbb1254663bb8dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68300
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure FSP S UPDs to allow coreboot to handle the lockdown.
The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).
The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch creates helper header file (ufs.h) for UFS to keep
required registers details and ACPI device id for UFS.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements voltage function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor voltage value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current SMBIOS for coreboot is missing processor info for Alder Lake
and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements max speed function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS max speed value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I09bcccc6f97238f7328224af8b852751114896fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Function 'setbits16' performs an 'OR' operation with the new data and
the origin register entry. This can lead to an incorrect value in the
register which can then lead to issues.
Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Makes it possible to configure the maximum allowed/supported DDR memory
frequency on a per mainboard basis.
Test
- Define maximum memory frequency in mainboard devicetree.cb
- Boot into Linux and run 'sudo dmidecode --type 17' to check memory
speed
- Boot into Linux and run 'phoronix-test-suite benchmark ramspeed'
Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68097
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
According to Intel document number 336561, GLK has UFS (0x1d),
so add the PCI interrupt.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel document number 336561, G, SD Card (0x1b)
does not exist on GLK, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To be able to change the MAC addresses, it is necessary that the
controllers are in D0 power state. As of FSP MR3, Intel has set the
controllers to D3 power state at the end of FSP-S TSN GbE
initialization. This patch sets the state back to D0 before the
programming of the MAC addresses.
Test:
- Build coreboot with FSP MR4 for mc_ehl2 mainboard
- Boot into Linux and check MAC addr via 'ip a'
Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
RaptorLake introduces the support of the Voltage Regulator Fast Vmode
feature. When enabled, it makes the SoC throttle when the current
exceeds the I_TRIP threshold. This threshold should be between
Iccmax.app and Iccmax and take into account the specification of the
Voltage Regulator of the system.
This change provides a mean to:
1. Enable the feature via the `vr_config->enable_fast_vmode'. If no
I_TRIP value is supplied FSPs picks an adapted I_TRIP value for
the current SoC assuming a Voltage Regulator error accuracy of
6.5%.
2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip'
field.
These new fields are considered independent from the other `vr_config'
fields so that the board configuration does not have to unnecessarily
supply other VR settings to enable Fast VMode.
Information about the Fast VMode Feature can be found in the following
Intel documents:
- 627270 ADL and RPL Processor Family Core and Uncore BIOS
Specification
- 724220 RaptorLake Platform Fast V-Mode
- 686872 RaptorLake Lake U P H Platform
BUG=b:243120082
BRANCH=firmware-brya-14505.B
TEST=Read I_TRIP from the Pcode and verify consistency with
a few `enable_fast_vmode' and `fast_vmode_i_trip' settings.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel Core i5-10210U can have the following IGD Device IDs
0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of
these IDs were not present in coreboot source nor hooked to the
common graphics driver. Add the missing IDs so that the graphics
driver will probe on the mentioned processor and detect the
framebuffer.
TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is
detected when using FSP GOP and libgfxinit.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The delayed return of certain fetch instruction from memory to
the UFS causes the OCP fabric to timeout on the transaction
and become non-responsive.
As recommended by the SoC and IP teams,program the
OCP fabric register to avoid the timeout in the OCP fabric.
This patch adds the following changes
1. Program the OCP fabric registers in the PS0 routine.
2. Move the ssdt contents of UFS to dsdt asl code to avoid
duplication of UFS device creation
BUG=b:240222922
TEST=Build and boot Nirwen UFS board, observe no system hang
during Chrome PLT test.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.
TEST: compile test and qemu run successfully with coreinfo
payload
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use just one function to get the chipset powerstate and add an argument
to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the
failure log accordingly.
TEST: compile tested and qemu emulation successfully run
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Guard sa_lock_pam with PAM0_REGISTER so it doesn't run on platforms
that don't select this.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5055d09c634851e9f869ab0b67a7bcab130f928c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66492
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo
Lake. This is used to select the options that Apollo Lake
requires, without the ones specific to a PCH as Apollo Lake
doesn't have a PCH.
This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for
Apollo Lake.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The fast SPI driver reports the BIOS window as reserved so that the OS
is aware of this region. Now that platforms which supports an extended
BIOS window are added to this driver, add the extended range as reserved
as well if it is enabled. And since this is now handled in the SPI
driver itself, remove the extended BIOS region reporting from
common systemagent code.
Change-Id: Ib5c735bffcb389be07c876d7b5b2d88c545a0b03
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
There are two classes of SPI controllers on Intel chipsets:
* generic usable SPI controllers
* SPI controller hosting the BIOS flash (fast SPI controller)
While the first class can be used for generic peripheral attachment the
second class mostly controls the BIOS flash and a TPM device (if
enabled). The generic SPI driver is not fully applicable to the fast SPI
controller. In addition, the fast SPI controller reports the reserved
MMIO range used for the BIOS flash mapping so that the OS is aware of
this range.
This patch moves the fast SPI controller of all known SoCs to the
fast SPI driver in common code. In addition, the PCI device for the
fast SPI controller is removed from the function 'spi_soc_devfn_to_bus'
as this is a callback of the generic SPI driver.
Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch provides a workaround which skips requesting IOM for D3 cold
entry sequence.
BUG=b:244082753
TEST=Verified MUX configuration after hot plugging Type-C devices on
Rex and MTL RVP boards.
Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit 7ef5376123.
Reason for revert: It was merged before its dependencies so now master is broken.
Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo
Updateable Product Data (UPD), enabling the Energy Efficient Turbo
feature by default. This feature prevents the cores from entering
Turbo frequency under heavy load.
As a result of this FSP change, coreboot explicitly disables this
feature to stay consistent with commit `caa5f59279e Revert
"soc/intel/alderlake: Enable energy efficiency turbo mode"'.
BRANCH=firmware-brya-14505.B
BUG=b:246831841
TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc'
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch adds power state 1/2/3 threshold setting interfaces
and pass the settings to FSP.
BUG=b:229803757
BRANCH=None
TEST=Add psi1threshold and psi2threshold to overridetree.cb and
enable FSP log to ensure the settings are incorrect.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
FSP-M is not run XIP so it can be compressed. This more than halves
the binary size. 364544 bytes -> 168616 bytes.
On the up/squared this also results in a 83ms speedup.
TESTED: up/squared boots.
Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure FSP S UPDs to allow coreboot to handle the lockdown.
The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).
The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Q0 stepping has a different ID than P1.
Reference: CML EDS Volume 1 (Intel doc #606599)
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.
For information on EOM status, please refer secton# 3.6.1 in doc#
612229.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
